A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique

A novel 64-bit hybrid radix-4 sparse-4 tree adder using clock-delayed (CD) footless domino logic is proposed. The adder operates at 6.4GHz with 181ps latency and it consumes 840mW at 1.2V in a standard 90nm CMOS technology. The adder latency is accurately measured by the programmable clock generated from delay-locked loop (DLL). Pseudo-exhaustive testing is applied so that all testable faults in this 64-bit adder are detected by just 23K patterns. This at-speed self testing technique is very useful for speed binning of high performance CPU.

[1]  Niraj K. Jha.  Testing for multiple faults in domino-CMOS logic circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  B. Nikolic,et al.  A 240ps 64b carry-lookahead adder in 90nm CMOS , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[3]  Shen-Iuan Liu,et al.  A 0.5–5-GHz Wide-Range Multiphase DLL With a Calibrated Charge Pump , 2007, IEEE Transactions on Circuits and Systems II: Express Briefs.

[4]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[5]  B. Bloechel,et al.  A 4GHz 300mW 64b integer execution ALU with dual supply voltages in 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[6]  Eric Lindbloom,et al.  Transition Fault Simulation , 1987, IEEE Design & Test of Computers.

[7]  Edward J. McCluskey,et al.  Condensed Linear Feedback Shift Register (LFSR) Testing—A Pseudoexhaustive Test Technique , 1986, IEEE Transactions on Computers.

[8]  Edward J. McCluskey.  Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.

[9]  Nandu Tendolkar,et al.  Novel techniques for achieving high at-speed transition fault test coverage for Motorola's microprocessors based on PowerPC/spl trade/ instruction set architecture , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[10]  S.H. Dhong,et al.  470 ps 64-bit parallel binary adder [for CPU chip] , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).