Exploiting BIST approach for two-pattern testing

Detection of delay and transistor stuck-open faults requires two-pattern tests. BIST provides a low-cost test solution. This paper exploits the BIST approach for two-pattern testing. The generation of a pseudo-deterministic test-pair sequence with LFSR was exploited. A three-step approach is proposed. First, a set of deterministic test-pair is generated to detect all robust path delay faults. Second, LFSR-based TPG configurations are calculated to have pre-generated test-pair embedded in a set of maximal length pseudo-random test sequences. Third, a global cost-optimal BIST solution for data path (using pseudo-deterministic TPGs) is proposed. The second step is formulated as a cluster-covering problem. The third step is formulated as an 0-1 ILP. Experimental results are presented to demonstrate the effectiveness of the proposed approach.

[1]  Patrick Girard,et al.  An optimized BIST test pattern generator for delay testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[2]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[3]  Xiaowei Li,et al.  An effective BIST scheme for delay testing , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).

[4]  Sandeep K. Gupta,et al.  Weighted random robust path delay testing of synthesized multilevel circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[5]  Jacob Savir.  Generator choices for delay test , 1995, Proceedings of the Fourth Asian Test Symposium.

[6]  Edward J. McCluskey,et al.  TWO-PATTERN TEST CAPABILITIES OF AUTONOMOUS TPG CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[7]  Yervant Zorian,et al.  On the generation of pseudo-deterministic two-patterns test sequence with LFSRs , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[8]  Constantin Halatsis,et al.  Accumulator-based BIST approach for stuck-open and delay fault testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[9]  Corot W. Starke,et al.  Built-In Test for CMOS Circuits , 1984, ITC.

[10]  Slawomir Pilarski,et al.  BIST and delay fault detection , 1993, Proceedings of IEEE International Test Conference - (ITC).

[11]  Susanta Chakraborty,et al.  New BIST techniques for universal and robust testing of CMOS stuck-open faults , 1997, Proceedings Tenth International Conference on VLSI Design.

[12]  Kiyoshi Furuya,et al.  Evaluations of various TPG circuits for use in two-pattern testing , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[13]  Jacob Savir,et al.  AC strength of a pattern generator , 1992, J. Electron. Test..

[14]  Karl Fuchs,et al.  A BIST approach to delay fault testing with reduced test length , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[15]  D. Michael Miller,et al.  BIST generators for sequential faults , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[16]  C.-J. Richard Shi,et al.  Cluster-cover: a theoretical framework for a class of VLSI-CAD optimization problems , 1998, TODE.

[17]  Sandeep K. Gupta,et al.  BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms , 1996, IEEE Trans. Computers.

[18]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[19]  Charles R. Kime,et al.  Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults , 1985, International Test Conference.