A flexible architecture for multi-standard LDPC decoders

Since Low-Density Parity-Check codes have near-capacity decoding performance and very high decoding throughput, they have been employed as FEC coding scheme in many transmission standards for wireless communication, such as IEEE 802.22n, IEEE 802.16e, DVB-S2, and DTMB. This trend triggers the need for so-called multi-standard LDPC decoders. In this paper, a flexible architecture that supports multiple code rates, variable block sizes and is code independent for block-LDPC codes is proposed, based on rearranged TPMP algorithm,. By implementing a dynamically reconfigurable RPPU, our proposed architecture can be configured into row update or column update mode by time-division multiplexing. Consequently, the decoder achieves a high area and power efficiency. To verify our proposed architecture, a novel LDPC decoder which supports IEEE802.16e standard has been implemented. The results on a 0.18 um CMOS process show that the decoder occupies an area of approximately 13.7 mm2 and runs correctly at an maximum operating frequency of 110 MHz, resulting in 98 Mbps decoding throughput1.

[1]  Mohammad M. Mansour,et al.  A Turbo-Decoding Message-Passing Algorithm for Sparse Parity-Check Matrix Codes , 2006, IEEE Transactions on Signal Processing.

[2]  Wang Ling Goh,et al.  A reconfigurable FPGA implementation of an LDPC decoder for unstructured codes , 2008, 2008 2nd International Conference on Signals, Circuits and Systems.

[3]  Joseph R. Cavallaro,et al.  A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards , 2008, 2008 IEEE International SOC Conference.

[4]  Shyh-Jye Jou,et al.  An LDPC Decoder Chip Based on Self-Routing Network for IEEE 802.16e Applications , 2008, IEEE Journal of Solid-State Circuits.

[5]  Bruno Bougard,et al.  Trade-off analysis of decoding algorithms and architectures for multi-standard LDPC decoder , 2008, 2008 IEEE Workshop on Signal Processing Systems.

[6]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[7]  Xin-Yu Shih,et al.  An 8.29 mm$^{2}$ 52 mW Multi-Mode LDPC Decoder Design for Mobile WiMAX System in 0.13 $\mu$m CMOS Process , 2008, IEEE Journal of Solid-State Circuits.