A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation

Side-channel attacks are one of the major concerns for security-enabled applications as they make use of information leaked by the physical implementation of the underlying cryptographic algorithm. Hence, reducing the side-channel leakage of the circuits realizing the cryptographic primitives is amongst the main goals of circuit designers. In this paper, we present a novel circuit concept, which decouples the main power supply from an internal power supply that is used to drive a single logic gate. The decoupling is done with the help of buffering capacitances integrated into semiconductor. We also introduce-compared to the previously known schemes-an improved decoupling circuit which reduces the crosstalk from the internal to the external power supply. The result of practical side-channel evaluation on a prototype chip fabricated in a 150nm CMOS technology shows a high potential of our proposed technique to reduce the side-channel leakages.

[1]  H. Barthelemy,et al.  On-Chip Voltage Regulator Protecting Against Power Analysis Attacks , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[2]  Amir Moradi,et al.  Moments-Correlating DPA , 2016, IACR Cryptol. ePrint Arch..

[3]  Stefan Mangard,et al.  Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints , 2005, CHES.

[4]  Andrey Bogdanov,et al.  PRESENT: An Ultra-Lightweight Block Cipher , 2007, CHES.

[5]  Daisuke Suzuki,et al.  Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style , 2006, CHES.

[6]  Patrick Schaumont,et al.  Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment , 2005, CHES.

[7]  Moti Yung,et al.  A Unified Framework for the Analysis of Side-Channel Key Recovery Attacks (extended version) , 2009, IACR Cryptol. ePrint Arch..

[8]  Thomas Zefferer,et al.  Evaluation of the Masked Logic Style MDPL on a Prototype Chip , 2007, CHES.

[9]  Ingrid Verbauwhede,et al.  Place and Route for Secure Standard Cell Design , 2004, CARDIS.

[10]  Stefan Mangard,et al.  Hardware Countermeasures against DPA ? A Statistical Analysis of Their Effectiveness , 2004, CT-RSA.

[11]  David Blaauw,et al.  Securing Encryption Systems With a Switched Capacitor Current Equalizer , 2010, IEEE Journal of Solid-State Circuits.

[12]  Pankaj Rohatgi,et al.  Template Attacks , 2002, CHES.

[13]  Martin Margala,et al.  An integrated countermeasure against differential power analysis for secure smart-cards , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[14]  Fernando Gehm Moraes,et al.  Current Mask Generation: A Transistor Level Security Against DPA Attacks , 2005, 2005 18th Symposium on Integrated Circuits and Systems Design.

[15]  FRANÇOIS-XAVIER STANDAERT,et al.  An Overview of Power Analysis Attacks Against Field Programmable Gate Arrays , 2006, Proceedings of the IEEE.

[16]  Fernando Gehm Moraes,et al.  Current Mask Generation: an Analog Circuit to Thwart DPA Attacks , 2005, VLSI-SoC.

[17]  Adi Shamir,et al.  Protecting Smart Cards from Passive Power Analysis with Detached Power Supplies , 2000, CHES.

[18]  Stefan Mangard,et al.  An AES Smart Card Implementation Resistant to Power Analysis Attacks , 2006, ACNS.

[19]  Ingrid Verbauwhede,et al.  A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[20]  Tim Güneysu,et al.  Generic Side-Channel Countermeasures for Reconfigurable Devices , 2011, CHES.

[21]  Thomas Plos,et al.  Evaluation of the Detached Power Supply as Side-Channel Analysis Countermeasure for Passive UHF RFID Tags , 2009, CT-RSA.

[22]  Vincent Rijmen,et al.  Secure Hardware Implementation of Nonlinear Functions in the Presence of Glitches , 2011, Journal of Cryptology.

[23]  Herve Barthelemy,et al.  A bi-channel voltage regulator protecting smart cards against power analysis attacks , 2009 .

[24]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[25]  Mario Kirschbaum,et al.  Evaluation of a DPA-Resistant Prototype Chip , 2009, 2009 Annual Computer Security Applications Conference.

[26]  Travis N. Blalock,et al.  An on-chip signal suppression countermeasure to power analysis attacks , 2004, IEEE Transactions on Dependable and Secure Computing.

[27]  Christof Paar,et al.  Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[28]  Stefan Mangard,et al.  Power analysis attacks - revealing the secrets of smart cards , 2007 .

[29]  I. Verbauwhede,et al.  A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards , 2002, Proceedings of the 28th European Solid-State Circuits Conference.

[30]  P. Rohatgi,et al.  A testing methodology for side channel resistance , 2011 .

[31]  Sylvain Guilley,et al.  The "Backend Duplication" Method , 2005, CHES.