As the IC industry embarks on a new process development, a short yield ramp cycle is crucial but challenging. Significant time and resources were consumed identifying yield limiting issues and finding the root causes to fix them. This paper describes the development and application of a yield enhancement methodology that identifies process challenging layout patterns and reduces process integration learning cycle time at both 65 nm and 90 nm technology nodes. This novel in-line method enables fabless companies to design test structures derived directly from actual product layout, and it helps the foundry to find killer defects quickly.