论文信息 - A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration

A 6.25Gb/s feed-forward equaliser in 0.18μm CMOS using delay locked loop with load calibration

A 6.25Gb/s 3-tap T/2-spaced feed-forward equaliser (FFE) is realized in 0.18μm CMOS Technology. The proposed FFE can be used to reduce the inter-symbol interference (ISI). A high frequency boost delay element using source capacitive degeneration is adopted to meet the high speed requirement. Additionally, a delay locked loop and a load calibration technique are used to overcome process variations. The chip including I/O pads occupies an area of 0.76×0.67mm2 and consumes a power of 108mW with 1.8V power supply. Post simulation results show that the proposed FFE works properly at 6.25Gb/s and more than 70% eye opening can be obtained.

Jun Feng | Yongsheng He | Qingsheng Hu

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