An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier

An 8bit two-step time-to-digital converter (TDC) with a novel digital switched ring-oscillator based time amplifier (TA) is demonstrated in 65nm CMOS. The proposed TA achieves a predictable and programmable gain without requiring any calibration. The implemented 8bit two-step TDC with a 16x TA gain achieves a time resolution of 2.6ps at 80MS/s conversion rate while consuming 2mW. The measured DNL and INL are 1.84LSB and 2.36LSB, respectively. The TDC area is 0.07mm2.

[1]  Alan F. Murray,et al.  IEEE International Solid-State Circuits Conference , 2001 .

[2]  Jaewook Kim,et al.  Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Antonio Liscidini,et al.  Time to digital converter based on a 2-dimensions Vernier architecture , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[4]  Jae-Yoon Sim,et al.  A 1GHz ADPLL with a 1.25ps minimum-resolution sub-exponent TDC in 0.18µm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[5]  Jae-Yoon Sim,et al.  A 1.25 ps Resolution 8b Cyclic TDC in 0.13 $\mu$m CMOS , 2012, IEEE Journal of Solid-State Circuits.

[6]  A. Abidi,et al.  A 9b, 1.25ps Resolution Coarse-Fine Time-to-Digital Converter in 90nm CMOS that Amplifies a Time Residue , 2007, 2007 IEEE Symposium on VLSI Circuits.

[7]  SeongHwan Cho,et al.  A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier , 2012, 2012 Symposium on VLSI Circuits (VLSIC).