Accelerated FPGA architecture design: Capabilities and limitations of analytical models

FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding of the capabilities and the limitations of the analytical models. In this paper, we use two representative architecture questions to provide such understanding. These two questions respectively investigate the optimization of a general-purpose FPGA architecture and the optimization of an application-specific FPGA architecture. For an optimized general purpose architecture, we show that the conclusions made by the analytical models are similar to the experimental techniques, with respect to three different design goals: area, delay and area-delay trade-off. This justifies the use of the analytical models in optimizing general-purpose FPGA architectures. We also find that the analytical models can not capture the behavior of ‘some’ applications that contain ‘discrete effects’. We present this later finding and the related explanations to show that the analytical models can not optimize application-specific architectures in some cases.

[1]  Wayne Luk,et al.  An Analytical Model Relating FPGA Architecture to Logic Density and Depth , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[2]  Rajeev Murgai,et al.  Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[3]  Steven J. E. Wilton,et al.  Wirelength modeling for homogeneous and heterogeneous FPGA architectural development , 2009, FPGA '09.

[4]  Peter Y. K. Cheung,et al.  Area estimation and optimisation of FPGA routing fabrics , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[5]  Jonathan Rose,et al.  Modeling routing demand for early-stage FPGA architecture development , 2008, FPGA '08.

[6]  Wayne Luk,et al.  Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[7]  Wayne Luk,et al.  Modeling post-techmapping and post-clustering FPGA circuit depth , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Steven J. E. Wilton,et al.  On the sensitivity of FPGA architectural conclusions to experimental assumptions, tools, and techniques , 2002, FPGA '02.

[9]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[10]  Wayne Luk,et al.  An analytical model describing the relationships between logic architecture and FPGA density , 2008, 2008 International Conference on Field Programmable Logic and Applications.

[11]  Rory A. Fisher,et al.  The Arrangement of Field Experiments , 1992 .

[12]  Fei Li,et al.  Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability , 2005, FPGA '05.

[13]  R. Plackett,et al.  THE DESIGN OF OPTIMUM MULTIFACTORIAL EXPERIMENTS , 1946 .

[14]  Donghyun Kim,et al.  A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[15]  Frank Vahid,et al.  Platune: a tuning framework for system-on-a-chip platforms , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Frank Vahid,et al.  Making good points: application-specific pareto-point generation for design space exploration using statistical methods , 2009, FPGA '09.

[17]  Farid N. Najm,et al.  Power estimation techniques for FPGAs , 2004 .

[18]  N. E. Jerger,et al.  DART : Fast and Flexible NoC Simulation using FPGAs , 2010 .

[19]  Desire L. Massart,et al.  Three-level screening designs for the optimisation or the ruggedness testing of analytical procedures , 1993 .

[20]  Peter Y. K. Cheung,et al.  FPGA Architecture Optimization Using Geometric Programming , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[21]  Jason Cong,et al.  Architecture evaluation for power-efficient FPGAs , 2003, FPGA '03.

[22]  Steven J. E. Wilton,et al.  An analytical model relating FPGA architecture parameters to routability , 2011, FPGA '11.