A 3D Packaging Technology for High-Density Stacked DRAM
暂无分享,去创建一个
[1] H. Kikuchi,et al. New three-dimensional integration technology using self-assembly technique , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[2] Peter Ramm,et al. Chip-to-wafer stacking technology for 3D system integration , 2003, 53rd Electronic Components and Technology Conference, 2003. Proceedings..
[3] K. Soejima,et al. A 3D Packaging Technology for 4 Gbit Stacked DRAM with 3 Gbps Data Transfer , 2006, 2006 International Electron Devices Meeting.
[4] M. Tago,et al. A novel "SMAFTI" package for inter-chip wide-band data transfer , 2006, 56th Electronic Components and Technology Conference 2006.