Two-Dimensional Power-Line Selection Scheme for Low Subthreshold-Current Multi-Gigabit DRAMs

Two-dimensional power-line selection scheme for an iterative CMOS circuit block, is proposed to reduce the subthreshold current. In this scheme, a block is divided into sub-blocks of two-dimensional arrangement and selectively energized by two-dimensional power-line selection. The scheme combined with dual word-line structure permits a drastic active current reduction to one sixteenth, from 363 mA to 22 mA, for a 16-Gb DRAM.

[1]  Mike Killian,et al.  A 33-ns 64-Mb DRAM with Master-Wordline Architecture , 1992, ESSCIRC '92: Eighteenth European Solid-State Circuits conference.

[2]  Kiyoo Itoh,et al.  Power Reduction Techniques in Megabit DRAM's , 1986 .

[3]  Takanori Saeki,et al.  A boosted dual world-line decoding scheme for 256 Mb DRAMs , 1992, 1992 Symposium on VLSI Circuits Digest of Technical Papers.

[4]  Robert H. Dennard.  Power-supply considerations for future scaled CMOS systems , 1989, International Symposium on VLSI Technology, Systems and Applications,.

[5]  S. Watanabe,et al.  Stand-by/active mode logic for sub-1 V 1 G/4 Gb DRAMs , 1993, Symposium 1993 on VLSI Circuits.

[6]  J. D. Meindl,et al.  Offset word line architecture for scaling DRAMs to the Gigabit level , 1987, 1987 Symposium on VLSI Circuits.

[7]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[8]  Masashi Horiguchi,et al.  Switched-source-impedance CMOS circuit for low standby subthreshold current giga-scale LSI's , 1993 .

[9]  M. Aoki,et al.  Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs) , 1993 .

[10]  S. M. Sze,et al.  Physics of semiconductor devices , 1969 .

[11]  Goro Kitsukawa,et al.  A 23-ns 1-Mb BiCMOS DRAM , 1990 .

[12]  K. Itoh,et al.  Subthreshold-current reduction circuits for multi-gigabit DRAM's , 1993, Symposium 1993 on VLSI Circuits.

[13]  M. Ukita,et al.  A 21-mW 4-Mb CMOS SRAM for battery operation , 1991 .

[14]  Toshio Takeshima,et al.  A 30-ns 256-Mb DRAM with a multidivided array structure , 1993 .

[15]  R. Scheuerlein,et al.  A 14-ns 14-Mb CMOS DRAM with 300-mW active power , 1992 .

[16]  Takeshi Sakata,et al.  Subthreshold-current reduction circuits for multi-gigabit DRAM's , 1994 .

[17]  Kiyoo Itoh.  Reviews and Prospects of Deep Sub-Micron DRAM Technology , 1991 .

[18]  Takayuki Kawahara,et al.  A circuit technology for sub-10-ns ECL 4-Mb BiCMOS DRAM's , 1991 .

[19]  Kiyoo Itoh,et al.  Sub-1-V swing internal bus architecture for future low-power ULSIs , 1993 .