DRAM technology perspective for gigabit era

Many challenges emerge as the DRAM enters into a generation of the gigabit density era. Most of the challenges come from the shrink technology which scales down minimum feature size by a factor of 0.84 per year. The need for higher performance to narrow the bandwidth mismatch between fast processors and slower memories and lower power consumption drives the DRAM technology toward smaller cell size, faster memory cell operation, less power consumption, and longer data retention times. In addition, increasingly complicated wafer processing requires simple process. In this paper, the challenges brought from the extremely small minimum feature, high performance, and simple wafer processing will be discussed. The solutions to overcome the challenges will be described focusing on the memory cell scheme, lithography, device, memory cell capacitor, and metallization.

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