A building block BIST methodology for SOC designs: a case study

System-on-Chip (SOC) designs use numerous and diverse embedded cores and memories. Very high system reliability requirements mandate greater than 99.9% ATPG chip manufacturing test coverage. Logic BIST and memory BIST are increasingly used for high system test coverage with additional constraints that some cores or pockets of user designed logic have to be functionally active during BIST. This paper describes the challenges of a design methodology to handle such SOC designs and the automated solutions that address these problems.

[1]  Brion L. Keller,et al.  Test methodologies and design automation for IBM ASICs , 1996, IBM J. Res. Dev..

[2]  James Sage,et al.  Test structure verification of logical BIST: problems and solutions , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[3]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[4]  B. L. Keller,et al.  Built-in self-test support in the IBM engineering design system , 1990 .

[5]  Vivek Chickermane,et al.  Addressing early design-for-test synthesis in a production environment , 1997, Proceedings International Test Conference 1997.

[6]  Ulrich Baur,et al.  Delay test of chip I/Os using LSSD boundary scan , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[7]  Janusz Rajski,et al.  Logic BIST for large industrial designs: real issues and case studies , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[8]  E. Kofi Vida-Torku,et al.  Designing for scan test of high performance embedded memories , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[9]  V. Chickermane,et al.  Integrating logic BIST in VLSI designs with embedded memories , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[10]  John A. Waicukauski,et al.  A Method for Generating Weighted Random Test Patterns , 1989, IBM J. Res. Dev..

[11]  Sujit Dey,et al.  High-level synthesis for testability: a survey and perspective , 1996, DAC '96.