Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS

This paper presents a novel low cost and double node upset (DNU) online self-recoverable latch design using radiation hardening by design (RHBD) technology. The latch mainly consists of 8 interlocked input-split inverters. Since all internal nodes are interlocked, if any of the possible node pairs occurs a DNU, the latch can restore back. Simulation results have demonstrated the DNU online self-recoverability and also demonstrated that the proposed latch design saves 71.68% transmission delay, 72.92% power dissipation and 93.69% comprehensive delay-power-area product (DPAP) on average, compared with the up-to-date DNU online self-recoverable latch designs.

[1]  Kiamal Z. Pekmestzi,et al.  DIRT latch: A novel low cost double node upset tolerant latch , 2017, Microelectron. Reliab..

[2]  Santosh Kumar Vishvakarma,et al.  Stable, Reliable, and Bit-Interleaving 12T SRAM for Space Applications: A Device Circuit Co-Design , 2017, IEEE Transactions on Semiconductor Manufacturing.

[3]  Vojin G. Oklobdzija,et al.  Low-Power Soft Error Hardened Latch , 2010, J. Low Power Electron..

[4]  Yuanqing Li,et al.  Double Node Upsets Hardened Latch Circuits , 2015, J. Electron. Test..

[5]  Ahmad Patooghy,et al.  Low energy single event upset/single event transient-tolerant latch for deep subMicron technologies , 2009, IET Comput. Digit. Tech..

[6]  Yiorgos Tsiatouhas,et al.  Soft error interception latch: double node charge sharing SEU tolerant design , 2015 .

[7]  Tianqi Wang,et al.  Low cost and highly reliable radiation hardened latch design in 65 nm CMOS technology , 2015, Microelectron. Reliab..

[8]  Huaguo Liang,et al.  Design of a Radiation Hardened Latch for Low-Power Circuits , 2014, 2014 IEEE 23rd Asian Test Symposium.

[9]  Huaguo Liang,et al.  Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Xiaoxuan She,et al.  SEU Tolerant Latch Based on Error Detection , 2012, IEEE Transactions on Nuclear Science.

[11]  Cecilia Metra,et al.  High-Performance Robust Latches , 2010, IEEE Transactions on Computers.

[12]  Fabrizio Lombardi,et al.  Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Zhengfeng Huang A high performance SEU-tolerant latch for nanoscale CMOS technology , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[14]  Huaguo Liang,et al.  A High Performance SEU Tolerant Latch , 2015, J. Electron. Test..

[15]  R.C. Baumann,et al.  Radiation-induced soft errors in advanced semiconductor technologies , 2005, IEEE Transactions on Device and Materials Reliability.

[16]  L. Chen,et al.  A Quatro-Based 65-nm Flip-Flop Circuit for Soft-Error Resilience , 2017, IEEE Transactions on Nuclear Science.

[17]  Ahmad Patooghy,et al.  Feedback Redundancy: A Power Efficient SEU-Tolerant Latch Design for Deep Sub-Micron Technologies , 2007, 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'07).

[18]  Mehdi B. Tahoori,et al.  Design of Defect and Fault-Tolerant Nonvolatile Spintronic Flip-Flops , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[19]  Ken Choi,et al.  Soft error tolerant latch design with low cost for nanoelectronic systems , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[20]  P. E. Dodd,et al.  Physics of Multiple-Node Charge Collection and Impacts on Single-Event Characterization and Soft Error Rate Prediction , 2013, IEEE Transactions on Nuclear Science.

[21]  Hai Huang,et al.  Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS Technology , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Spyros Tragoudas,et al.  A Highly Robust Double Node Upset Tolerant latch , 2016, 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).

[23]  Huaguo Liang,et al.  A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology , 2015, IEICE Trans. Electron..

[24]  Kiamal Z. Pekmestzi,et al.  DONUT: A Double Node Upset Tolerant Latch , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.

[25]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[26]  Robert C. Aitken,et al.  Impact of voltage scaling on nanoscale SRAM reliability , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[27]  Ken Choi,et al.  Low cost and highly reliable hardened latch design for nanoscale CMOS technology , 2012, Microelectron. Reliab..

[28]  Ken Choi,et al.  High Performance, Low Cost, and Robust Soft Error Tolerant Latch Designs for Nanoscale CMOS Technology , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.