Theory and Implementation of a Computationally Efficient Decimation Filter for Power-Aware Embedded Systems

As analog-to-digital converters become faster, this will allow them to become closer to their intended sensor. This will foster an environment that will continue to allow a paradigm shift in which digital systems replace analog ones, thus mitigating many nonideal effects, lowering costs, and providing more compact computational platforms. In parallel with this trend, the importance of decimation filters will continue to expand, as the high-speed data will need to be downsampled prior to ingestion by a decision-making element, such as a digital signal processor running constant false alarm rate (CFAR) algorithms, neural networks, and the like. Ideally, these decimation filters should have as much stopband attenuation as possible and should not be hindered by timing bottlenecks. However, on a fixed-point processor, like a field-programmable gate array (FPGA), finite word-length effects are in opposition to this goal. To break this nexus, this paper employs a revolutionary integerization technique based on multidimensional continued fractions strategically coupled with an efficient multiplierless architecture design strategy. Multidimensional continued fractions have been known within the mathematical community for some time, which include the popular Furtwangler algorithm and the ordered Jacobi-Perron algorithm, but have been left unexplored in the engineering community until recently. Simultaneous rational representations (SRRs) are another member of the multidimensional continued fraction family and are employed here to create fixed integer transforms with computationally optimal representations. In addition, this paper also focuses on hardware implementations in low-cost FPGAs or application-specific integrated circuits, which benefit from multiplierless implementation to save hardware real estate. From a computational perspective, carefully choosing how to represent the coefficients of a transform may have dramatic effects on how many operations are consumed to implement it. In a low-order example, the number seven may be expressed as 23-20 or 22 +21+20. This concept coupled with SRRs is explored in this paper to yield low-power high-speed implementations for embedded systems

[1]  Mark B. Yeary,et al.  A DSP-based mixed-signal waveform generator , 2004, IEEE Transactions on Instrumentation and Measurement.

[2]  Kishore A. Kotteri,et al.  Design of multiplierless, high-performance, wavelet filter banks with image compression applications , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Chi-Ying Tsui,et al.  Power efficient technology decomposition and mapping under an extended power consumption model , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Peter Grant.  Multirate signal processing , 1996 .

[5]  Jerzy W. Rozenblit,et al.  A new framework for power estimation of embedded systems , 2005, Computer.

[6]  Mark B. Yeary,et al.  Design of an embedded DSP system for a fuel cell inverter , 2002, 2002 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[7]  Mark B. Yeary,et al.  Design and implementation of a mixed-signal embedded DSP system , 2001, 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221).

[8]  Joan L. Mitchell,et al.  Vectorized transforms in scalar processors , 2002, IEEE Signal Process. Mag..

[9]  Nasser Kehtarnavaz,et al.  DSP-based hierarchical neural network modulation signal classification , 2003, IEEE Trans. Neural Networks.

[10]  Michael D. Zoltowski,et al.  The effects of finite bit precision for a VLSI implementation of the constant modulus algorithm , 1999, 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).

[11]  Mark B. Yeary,et al.  Design of a CORDIC processor for mixed-signal A/D conversion , 2002, IEEE Trans. Instrum. Meas..

[12]  Ephraim Feig,et al.  Fast algorithms for the discrete cosine transform , 1992, IEEE Trans. Signal Process..

[13]  Michele Marchesi,et al.  Digital filters design by simulated annealing , 1989 .

[14]  Tolga Çiloglu,et al.  A new approach to discrete coefficient FIR digital filter design by simulated annealing , 1993, 1993 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[15]  M. Yeary,et al.  A computationally efficient decimation filter design for embedded systems , 2004, Proceedings of the 21st IEEE Instrumentation and Measurement Technology Conference (IEEE Cat. No.04CH37510).

[16]  P. Shanti Sastry,et al.  New algorithms for learning and pruning oblique decision trees , 1999, IEEE Trans. Syst. Man Cybern. Part C.

[17]  P. Vaidyanathan.  Multirate Systems And Filter Banks , 1992 .

[18]  Makoto Ohtsuki,et al.  Parallelogram Tilings and Jacobi-Perron Algorithm , 1994 .

[19]  Fredric J. Harris,et al.  Multirate Signal Processing for Communication Systems , 2004 .

[20]  Jennifer Q. Trelewicz,et al.  Multidimensional rational approximations with an application to linear transforms , 2004, IEEE Transactions on Signal Processing.

[21]  Joan Carletta,et al.  Quantized FIR filter design using compensating zeros , 2003, IEEE Signal Process. Mag..

[22]  D. M. Hardcastle,et al.  On almost everywhere strong convergence of multi-dimensional continued fraction algorithms , 2000, Ergodic Theory and Dynamical Systems.

[23]  Ravi Kothari,et al.  Classifiability based pruning of decision trees , 2001, IJCNN'01. International Joint Conference on Neural Networks. Proceedings (Cat. No.01CH37222).

[24]  Franz Franchetti,et al.  SPIRAL: Code Generation for DSP Transforms , 2005, Proceedings of the IEEE.

[25]  N. Kehtarnavaz,et al.  A DSP-based implementation of a WCDMA reverse link design , 2001, 2001 IEEE Emerging Technologies Symposium on BroadBand Communications for the Internet Era. Symposium Digest (Cat. No.01EX508).

[26]  Mark B. Yeary,et al.  A Low-Cost Embedded System For Internet Based Power Measurement , 2003, Int. J. Inf. Technol. Decis. Mak..

[27]  A. Brentjes,et al.  Multi-dimensional continued fraction algorithms , 1981 .

[28]  J. I. Sewell.  High performance front-end signal processing: system design aids , 1992 .

[29]  Konstantinos Konstantinides,et al.  Image and Video Compression Standards: Algorithms and Architectures , 1997 .

[30]  Mark B. Yeary,et al.  Adaptive IIR filter design for single sensor applications , 2002, IEEE Trans. Instrum. Meas..

[31]  Joan Carletta,et al.  Quantized FIR filter design using compensating zeros , 2003 .

[32]  T. Moon,et al.  Mathematical Methods and Algorithms for Signal Processing , 1999 .

[33]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[34]  James C. Hoe,et al.  Custom-optimized multiplierless implementations of DSP algorithms , 2004, ICCAD 2004.

[35]  Mark Yeary,et al.  Computationally efficient wavelet decomposition/reconstruction for embedded systems , 2002, Proceedings of 2002 IEEE 10th Digital Signal Processing Workshop, 2002 and the 2nd Signal Processing Education Workshop..