Variation tolerant on-chip degradation sensors for dynamic reliability management systems

Abstract Aggressive technology scaling has inevitably led reliability become a key concern for modern ICs. With commonly existing Process, Voltage, and Temperature (PVT) variations inside a chip, lifetime reliability assurance becomes hardly possible without Dynamic Reliability Management (DRM). In order to maintain a chip’s lifetime reliability specification, we propose a novel DRM framework in this paper, which predicts hardware aging and take the necessary actions in order to extend the system lifetime and/or prevent system failure. To collect reliability data from the circuits we introduce aging sensor circuitries able to sense transistor’s threshold voltage degradation caused by NBTI/HCI stresses. Aging sensors are carefully designed under the context of severe PVT variations for current and future technologies, and simulations based on the TSMC 65 nm technology library show that a low temperature sensitivity as low as 0.29 mV/°C is achieved by our design, compared with 0.51 mV/°C for NBTI sensor and 0.325 mV/°C for HCI sensor from prior work; and a VDD variation sensitivity of 0.24 mV/mV is achieved by our design. The temperature deviation of our design is limited to 17% for extreme conditions and is about 5% at room temperature range, and the deviation of voltage is maximum 7% for extreme conditions and it is negligible at standard VDD.