A Simulation Tool for Rapid Investigation of Trends in 3-DIC Performance and Power Consumption

In order to compare the costs and the benefits of 2-D and 3-D integrated circuits (3-DICs) technologies, a compact simulation tool for 3-DIC system evaluation and design space exploration is presented. The simulator is implemented in the MATLAB, and is composed of several modules, including a compact 3-DIC wire-length distribution, a wire pitch and repeater insertion module, a 2-D and 3-DIC power supply noise estimation module, and a finite-difference thermal simulator. The simulator is validated against published data for several commercial 2-D processors at the 65-, 45-, and 32-nm nodes. In order to quantify the benefits of both 2-D and 3-D integration approaches, a 32-nm CPU core is modeled, and the impact of several technology parameters, including interlayer dielectric material, on-chip wire material, die thickness, and cooling solution, is explored. The results suggest that the 3-D integration may provide a significant power reduction for the 32-nm test case, but more aggressive cooling solutions must be employed to maintain the same clock frequency due to the increased areal power density of the 3-D CPU.

[1]  Payman Zarkesh-Ha,et al.  Impact of three-dimensional architectures on interconnects in gigascale integration , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Keith A. Bowman,et al.  Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI) , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[4]  Reza Sarvari,et al.  Intsim: a CAD tool for optimization of multilevel interconnect networks , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.

[5]  M. Bakir,et al.  Novel Electrical and Fluidic Microbumps for Silicon Interposer and 3-D ICs , 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[6]  Christoph Adelmann,et al.  Alternative metals for advanced interconnects , 2014, IEEE International Interconnect Technology Conference.

[7]  G. Beyer,et al.  Reliability of copper low-k interconnects , 2010 .

[8]  Robert E. Peale,et al.  Surface and grain-boundary scattering in nanometric Cu films , 2010 .

[9]  Ken Smits,et al.  Penryn: 45-nm next generation Intel® core™ 2 processor , 2007, 2007 IEEE Asian Solid-State Circuits Conference.

[10]  Gang Huang,et al.  Power Delivery for 3-D Chip Stacks: Physical Modeling and Design Implication , 2012, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[11]  R. Pease,et al.  High-performance heat sinking for VLSI , 1981, IEEE Electron Device Letters.

[12]  O. Rozeau,et al.  Monolithic 3D integration: A powerful alternative to classical 2D scaling , 2014, 2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

[13]  Robert S. Patti,et al.  Three-Dimensional Integrated Circuits and the Future of System-on-Chip Designs , 2006, Proceedings of the IEEE.

[14]  Jianyong Xie,et al.  Electrical-Thermal Co-Simulation of 3D Integrated Systems With Micro-Fluidic Cooling and Joule Heating Effects , 2011, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[15]  J. Lau.  Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration , 2011, 2011 International Symposium on Advanced Packaging Materials (APM).

[16]  Muhannad S. Bakir,et al.  Evaluation of 3DICs and fabrication of monolithic interlayer vias , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[17]  Sung Kyu Lim,et al.  Through-silicon-via aware interconnect prediction and optimization for 3D stacked ICs , 2009, SLIP '09.

[18]  M. Bakir,et al.  Thermal Design and Constraints for Heterogeneous Integrated Chip Stacks and Isolation Technology Using Air Gap and Thermal Bridge , 2014, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[19]  J. Jopling,et al.  High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).

[20]  Rajesh Kumar,et al.  A family of 45nm IA processors , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[21]  Dirk Stroobandt,et al.  The interpretation and application of Rent's rule , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[22]  Yue Zhang,et al.  Within-tier cooling and thermal isolation technologies for heterogeneous 3D ICs , 2013, 2013 IEEE International 3D Systems Integration Conference (3DIC).

[23]  Anthony S. Oates,et al.  Strategies to Ensure Electromigration Reliability of Cu/Low-k Interconnects at 10 nm , 2015 .

[24]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[25]  P. Bai,et al.  A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[26]  Marcelo Yuffe,et al.  The Implementation of the 65nm Dual-Core 64b Merom Processor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[27]  C. Kim,et al.  Electromigration failure in ultra-fine copper interconnects , 2003 .

[28]  Muhannad S. Bakir,et al.  Silicon Micropin-Fin Heat Sink With Integrated TSVs for 3-D ICs: Tradeoff Analysis and Experimental Testing , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[29]  Marcelo Yuffe,et al.  A fully integrated multi-CPU, GPU and memory controller 32nm processor , 2011, 2011 IEEE International Solid-State Circuits Conference.

[30]  P. Zarkesh-Ha,et al.  On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rule , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).