Generation of test cases for hardware design verification of a super-scalar Fetch Processor

We describe a method to generate test cases (or test programs) for hardware design verification. The proposed method uses non-functional errors defined over a software model of the specification to guide the generation of test programs. Application of the proposed method to the Hal. super-scalar Fetch Processor is also described. For this design, we present experimental results to demonstrate the effectiveness of the method in achieving a high design error coverage with relatively short test programs.

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