VLSI architectures for digital image coding

A number of high-performance VLSI architectures for real-time image coding applications are described. In particular, attention is focused on circuits for computing the 2D DCT (discrete cosine transform) and for 2-D vector quantization. The former circuits are based on Winograd algorithms and compromise a number of bit-level systolic arrays with a bit-serial, word-parallel input. The latter circuits exhibit a similar data organization and consist of a number of inner product array circuits. Both circuits are highly regular and allow extremely high data rates to be achieved through extensive use of parallelism.<<ETX>>

[1]  Huifang Sun,et al.  Image Sequence Coding Using Vector Quantization , 1986, IEEE Trans. Commun..

[2]  R. Gray,et al.  Vector quantization , 1984, IEEE ASSP Magazine.

[3]  John V. McCanny,et al.  Bit-level systolic array implementation of the winograd fourier transform algorithm , 1985 .

[4]  John V. McCanny,et al.  Systolic array system for vector quantization using transformed sub-band coding , 1988, [1988] Proceedings. International Conference on Systolic Arrays.

[5]  Francis Jutand,et al.  A one chip VLSI for real time two-dimensional discrete cosine transform , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[6]  C. Smith,et al.  Adaptive Coding of Monochrome and Color Images , 1977, IEEE Trans. Commun..

[7]  Jeremy S. Ward.  Number theoretic techniques applied to algorithms and architectures for digital signal processing , 1983 .

[8]  Richard E. Blahut,et al.  Fast Algorithms for Digital Signal Processing , 1985 .

[9]  B. J. Stanier,et al.  Fast discrete cosine transform algorithm for systolic arrays , 1983 .

[10]  S. Winograd.  On computing the Discrete Fourier Transform. , 1976, Proceedings of the National Academy of Sciences of the United States of America.

[11]  N. Ahmed,et al.  Discrete Cosine Transform , 1996 .