Analyzing static and dynamic write margin for nanometer SRAMs

This paper analyzes write ability for SRAM cells in deeply scaled technologies, focusing on the relationship between static and dynamic write margin metrics. Reliability has become a major concern for SRAM designs in modern technologies. Both local mismatch and scaled VDD degrade read stability and write ability. Several static approaches, including traditional SNM, BL margin, and the N-curve method, can be used to measure static write margin. However, static approaches cannot indicate the impact of dynamic dependencies on cell stability. We propose to analyze dynamic write ability by considering the write operation as a noise event that we analyze using dynamic stability criteria. We also define dynamic write ability as the critical pulse width for a write. By using this dynamic criterion, we evaluate the existing static write margin metrics at normal and scaled supply voltages and assess their limitations. The dynamic write time metric can also be used to improve the accuracy of VCCmin estimation for active VDD scaling designs.

[1]  N. Vallepalli,et al.  A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply , 2005, IEEE Journal of Solid-State Circuits.

[2]  J. Lohstroh.  Static and dynamic noise margins of logic circuits , 1979 .

[3]  N. Planes,et al.  A New Combined Methodology for Write-Margin Extraction of Advanced SRAM , 2007, 2007 IEEE International Conference on Microelectronic Test Structures.

[4]  M. Nomura,et al.  Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[5]  Sani R. Nassif,et al.  Statistical analysis of SRAM cell stability , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[6]  Peng Li,et al.  Tracing SRAM separatrix for dynamic noise margin analysis under device mismatch , 2007, 2007 IEEE International Behavioral Modeling and Simulation Workshop.

[7]  Kaushik Roy,et al.  Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Kenneth L. Shepard,et al.  Cell characterization for noise stability , 2000, Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044).

[9]  S. Kosonocky,et al.  Fluctuation limits & scaling opportunities for CMOS SRAM cells , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[10]  M. Khellah,et al.  Effect of Power Supply Noise on SRAM Dynamic Stability , 2007, 2007 IEEE Symposium on VLSI Circuits.

[11]  W. Dehaene,et al.  Read Stability and Write-Ability Analysis of SRAM Cells for Nanometer Technologies , 2006, IEEE Journal of Solid-State Circuits.

[12]  C. Wann,et al.  SRAM cell design for stability methodology , 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

[13]  S. Nassif,et al.  Analytical Modeling of SRAM Dynamic Stability , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.