Design of Approximate Multiplierless DCT with CSD Encoding for Image Processing

This paper presents a multiplierless discrete cosine transforms (DCT) design with approximate canonical signed digit (CSD) encoding for image processing. Two approximation strategies on CSD encoding are proposed in constant multiplication. Based on these two coding approaches, an approximate DCT architecture is presented by taking advantage of the correlation between adjacent pixels of image data. Higher frequency coefficients are gradually ignored from the calculation due to the energy compaction property. Four approximate DCT architectures are thus proposed representing different accuracy levels. The proposed DCTs are implemented using 0.18μm standard CMOS process. The simulation results indicate that the proposed ADCT reduces 51.5% power and 30.0% area with a PSNR penalty of 1.6dB when compared with the traditional design. For lossy applications which allow lower computational accuracy, ADCT-III achieves 70.0% and 43.9% reduction on the power consumption and area, respectively, at a cost of 11.7 dB accuracy loss.