System-In-Package (SIP) enables flexible and low cost integration of multiple components such as memory, logic or passives in a single package. However, SIP performances are today limited for high performances applications such as FPGA, processor or GPU in which high bandwidth communication between the elements of the system is required. The use of an intermediate carrier such as Silicon Interposer between IC chips and substrate resolve the bandwidth bottleneck by increasing the I/Os number. Indeed, Si Interposer combines fine pitch μBumps and high density routing for fast and high bandwidth interconnection between mounted chips. Low cost semi-additive electrochemical plating process (ECP) is often used for interposer routing processing [1]. Damascene process is an alternative allowing for an improved reliability (use of barrier between Cu and dielectric) and better line pitch scalability [2]. However, the use of thin lines characteristic of standard damascene technology such as 65 nm Back-End-Of-Line (BEOL), impact overall signal transmission performances because of their relative high resistance compare with ECP approach. In this work, impacts of Cu lines dimensions and line neighboring onto system bandwidth and crosstalk are first simulated. The output allows for optimal performances interposer damascene interconnect which process and characterization are described in a second part.