Control system communication architecture for power electronic building blocks

Recent developments in SiC power devices have enabled the development of Power Electronic Building Blocks (PEBBs) having greater switching frequencies than Si-based devices such as IGBTs, but also require shorter time scales in their corresponding control systems. At the same time, system designers are scaling up modularized converter systems, such as the Modular Multilevel Converter, which can now comprise hundreds of PEBBs. Both of those trends present the need to evaluate architectural tradeoffs and communication requirements for hardware realizations of the Universal Controller Architecture. The control network should be designed to have minimal round-trip latency and maximal scalability. In this paper we present the results of a study to determine the most appropriate communication architecture and routing for networked PEBB control systems.

[1]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[2]  T. Ericsen,et al.  Power Electronic Building Blocks-a systematic approach to power electronics , 2000, 2000 Power Engineering Society Summer Meeting (Cat. No.00CH37134).

[3]  Herbert Ginn,et al.  Control/protection architecture for power electronic converters , 2010, 2010 Record of Conference Papers Industry Applications Society 57th Annual Petroleum and Chemical Industry Conference (PCIC).

[4]  Nachiket Kapre,et al.  Hoplite: Building austere overlay NoCs for FPGAs , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[5]  William J. Dally,et al.  GOAL: a load-balanced adaptive routing algorithm for torus networks , 2003, ISCA '03.

[6]  Steven Swanson,et al.  Latency-Optimized Networks for Clustering FPGAs , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[7]  D. Boroyevich,et al.  Open modular power electronics building blocks for utility power system controller applications , 2003, IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC '03..

[8]  Nachiket Kapre,et al.  Implementing FPGA Overlay NoCs Using the Xilinx UltraScale Memory Cascades , 2017, 2017 IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[9]  Herbert L. Ginn,et al.  Real-Time Distributed Coordination of Power Electronic Converters in a DC Shipboard Distribution System , 2017, IEEE Transactions on Energy Conversion.

[10]  Ron Sass,et al.  AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks , 2009, 2009 17th IEEE Symposium on Field Programmable Custom Computing Machines.