Design of an Asynchronous Data Cache with FIFO Buffer for Write Back Mode

AbstractIn this paper, we propose the data cache architecture with a write buffer for a 32bit asynchronous embedded processor. The data cache consists of CAM and data memory. It accelerates data up lood cycle between the processor and the main memory that improves processor performance. The proposed data cache has 8 KB cache memory. The cache uses the 4-way set associative mapping with line size of 4 words (16 bytes) and pseudo LRU replacement algorithm for data replacement in the memory. Dirty register and write buffer is used for write policy of the cache. The designed data cache is synthesized to a gate level design using 0.13-㎛ process. Its average hit rate is 94%. And the system performance has been improved by 46.53%. The proposed data cache with write buffer is very suitable for a 32-bit asynchronous processor. ■ keyword :∣Data Cache∣Write Buffer∣Asynchronous FIFO ∣Asynchronous System ∣ * 이 논문은 2008년도 충북대학교 학술연구지원사업의 연구비 지원에 의하여 연구되었음접수번호 : #100531-003접수일자 : 2010년 05월 31일 심사완료일 : 2010년 06월 18일교신저자 : 박종민, e-mail : jmpark@hbt.cbnu.ac.kr