The Architecture of the MU5 Processor

The design of the MU5 processor was approached through its order code, this being the natural interface between software requirements and hardware organisation. Full interplay between the two aspects was considered vital throughout the design. Efficient processing of high-level language programs was the prime target. In ‘number crunching’ applications, this meant a fast execution rate for the high-level language programs. However, the system envisaged would be interactive, and to combat the system overheads this entails, it was considered important to produce small compilers and compiled programs. Thus, an order code was sought which satisfied the following conditions (1) Generation of efficient code by compilers must be easy (2) Programs must be compact (3) The instruction set must allow a pipeline organisation of the CPU leading to a fast execution rate (4) Information on the nature of operands (scalar or array element, for example) should be available to allow optimal buffering of operands.