Synthesis of Asynchronous Hardware from Petri Nets

As semiconductor technology strides towards billions of transistors on a single die, problems concerned with deep sub-micron process features and design productivity call for new approaches in the area of behavioural models. This paper focuses on some of recent developments and new opportunities for Petri nets in designing asynchronous circuits such as synthesis of asynchronous control circuits from large Petri nets generated from front-end specifications in hardware description languages. These new methods avoid using full reachability state space for logic synthesis. They include direct mapping of Petri nets to circuits, structural methods with linear programming, and synthesis from unfolding prefixes using SAT solvers.

[1]  Kenneth L. McMillan,et al.  Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits , 1992, CAV.

[2]  Alexandre Yakovlev,et al.  Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems , 1990 .

[3]  Walter Vogler,et al.  An Improvement of McMillan's Unfolding Algorithm , 1996, Formal Methods Syst. Des..

[4]  Anna Philippou,et al.  Tools and Algorithms for the Construction and Analysis of Systems , 2018, Lecture Notes in Computer Science.

[5]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[6]  Alexandre Yakovlev,et al.  Verification of asynchronous circuits using time Petri net unfolding , 1996, DAC '96.

[7]  Michael Kishinevsky,et al.  Concurrent hardware : the theory and practice of self-timed design , 1993 .

[8]  Wolfgang Fichtner,et al.  Self-timed ring for globally-asynchronous locally-synchronous systems , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[9]  F. Xia,et al.  Asynchronous circuit synthesis via direct translation , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[10]  Josep Carmona,et al.  A structural encoding technique for the synthesis of asynchronous circuits , 2001, Proceedings Second International Conference on Application of Concurrency to System Design.

[11]  Rajeev Alur,et al.  A Temporal Logic of Nested Calls and Returns , 2004, TACAS.

[12]  Doug A. Edwards,et al.  Balsa: An Asynchronous Hardware Synthesis Language , 2002, Comput. J..

[13]  Tadao Murata,et al.  Petri nets: Properties, analysis and applications , 1989, Proc. IEEE.

[14]  R. Milner,et al.  Bigraphical Reactive Systems , 2001, CONCUR.

[15]  Wolfgang Reisig,et al.  Lectures on Petri Nets II: Applications , 1996, Lecture Notes in Computer Science.

[16]  Walter Vogler,et al.  Decomposition in Asynchronous Circuit Design , 2002, Concurrency and Hardware Design.

[17]  Grzegorz Rozenberg,et al.  Concurrency and Hardware Design , 2002, Lecture Notes in Computer Science.

[18]  Alexander B. Smirnov,et al.  Towards synthesis of monotonic asynchronous circuits from signal transition graphs , 2001, Proceedings Second International Conference on Application of Concurrency to System Design.

[19]  Maciej Koutny,et al.  Towards an Efficient Algorithm for Unfolding Petri Nets , 2001, CONCUR.

[20]  Keijo Heljanko,et al.  Using Logic Programs with Stable Model Semantics to Solve Deadlock and Reachability Problems for 1-Safe Petri Nets , 1999, Fundam. Informaticae.

[21]  Yervant Zorian,et al.  2001 Technology Roadmap for Semiconductors , 2002, Computer.

[22]  Alex Kondratyev,et al.  Design of Asynchronous Circuits Using Synchronous CAD Tools , 2002, IEEE Des. Test Comput..

[23]  Manuel Silva Suárez,et al.  Linear Algebraic and Linear Programming Techniques for the Analysis of Place or Transition Net Systems , 1996, Petri Nets.

[24]  Alexandre Yakovlev,et al.  Towards asynchronous A-D conversion , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[25]  Albert Koelmans,et al.  Petri Nets and Digital Hardware Design , 1998 .

[26]  Alexei Semenov.  Verification and synthesis of asynchronous control circuits using petri net unfoldings , 1997 .

[27]  Kay Soon Low,et al.  Token Ring Arbiters: An Exercise in Asynchronous Logic Design with Petri Nets , 1995 .

[28]  Kees van Berkel,et al.  Handshake Circuits: An Asynchronous Architecture for VLSI Programming , 1993 .

[29]  Maciej Koutny,et al.  Detecting state coding conflicts in STGs using integer programming , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[30]  Alexandre Yakovlev.  Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets , 1998, Formal Methods Syst. Des..

[31]  Josep Carmona,et al.  Input/Output Compatibility of Reactive Systems , 2002, FMCAD.

[32]  William J. Dally,et al.  Digital systems engineering , 1998 .

[33]  Javier Esparza,et al.  A polynomial-time algorithm for checking consistency of free-choice signal transition graphs , 2003, Third International Conference on Application of Concurrency to System Design, 2003. Proceedings..

[34]  Javier Esparza,et al.  Decidability and Complexity of Petri Net Problems - An Introduction , 1996, Petri Nets.

[35]  Alexandre Yakovlev,et al.  Designing an asynchronous pipeline token ring interface , 1995, Proceedings Second Working Conference on Asynchronous Design Methodologies.

[36]  Josep Carmona,et al.  ILP Models for the Synthesis of Asynchronous Control Circuits , 2003, ICCAD 2003.

[37]  Luciano Lavagno,et al.  Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[38]  Maciej Koutny,et al.  Logic Synthesis Avoiding State Space Explosion , 2003 .

[39]  Alexandre Yakovlev,et al.  Monotonic circuits with complete acknowledgement , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..

[40]  Alexandre Yakovlev,et al.  STG optimisation in the direct mapping of asynchronous circuits , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[41]  Eike Best,et al.  PEP - More than a Petri Net Tool , 1996, TACAS.

[42]  Jörg Desel,et al.  Reachability in Cyclic Extended Free-Choice Systems , 1993, Theor. Comput. Sci..

[43]  Alex Yakovlev,et al.  Asynchronous circuit synthesis by direct mapping: interfacing to environment , 2002, Proceedings Eighth International Symposium on Asynchronous Circuits and Systems.

[44]  Jordi Cortadella,et al.  Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[45]  Luciano Lavagno,et al.  A region-based theory for state assignment in speed-independent circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[46]  Carl-Johan H. Seger,et al.  Design of Asynchronous Circuits , 1995 .

[47]  Antti Valmari,et al.  A stubborn attack on state explosion , 1990, Formal Methods Syst. Des..

[48]  Doug A. Edwards,et al.  A burst-mode oriented back-end for the Balsa synthesis system , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[49]  Montek Singh,et al.  A Power-Efficient Duplex Communication System , 2000 .

[50]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[51]  Maciej Koutny,et al.  Detecting state coding conflicts in STG unfoldings using SAT , 2003, Third International Conference on Application of Concurrency to System Design, 2003. Proceedings..

[52]  Maciej Koutny,et al.  Parallelisation of the Petri Net Unfolding Algorithm , 2002, TACAS.

[53]  Hugo De Man,et al.  Optimized synthesis of asynchronous control circuits from graph-theoretic specifications , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[54]  Maciej Koutny,et al.  LP Deadlock Checking Using Partial Order Dependencies , 2000, CONCUR.

[55]  Wolfgang Reisig,et al.  Lectures on Petri Nets I: Basic Models , 1996, Lecture Notes in Computer Science.

[56]  Luciano Lavagno,et al.  Automated synthesis of micro-pipelines from behavioral Verilog HDL , 2000, Proceedings Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000) (Cat. No. PR00586).

[57]  Chris J. Myers,et al.  Synthesis of speed independent circuits based on decomposition , 2004, 10th International Symposium on Asynchronous Circuits and Systems, 2004. Proceedings..

[58]  Hemangee K. Kapoor,et al.  Verification and implementation of delay-insensitive processes in restrictive environments , 2004, Proceedings. Fourth International Conference on Application of Concurrency to System Design, 2004. ACSD 2004..

[59]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[60]  Wolfgang Reisig,et al.  Application and Theory of Petri Nets 1996 , 1996, Lecture Notes in Computer Science.

[61]  Kousha Etessami,et al.  Optimizing Büchi Automata , 2000, CONCUR.

[62]  Sharad Malik,et al.  The Quest for Efficient Boolean Satisfiability Solvers , 2002, CAV.

[63]  C. Petri.  Kommunikation mit Automaten , 1962 .

[64]  N. S. Barnett,et al.  Private communication , 1969 .

[65]  RENA DAVID,et al.  Modular Design of Asynchronous Circuits Defined by Graphs , 1977, IEEE Transactions on Computers.

[66]  Maciej Koutny,et al.  Canonical prefixes of Petri net unfoldings , 2002, Acta Informatica.

[67]  Luciano Lavagno,et al.  Logic Synthesis for Asynchronous Controllers and Interfaces , 2002 .

[68]  R. Krenz,et al.  Design, Analysis and Implementation of a Self-Timed Duplex Communication System , 2002 .

[69]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[70]  Lee A. Hollaar.  Direct Implementation of Asynchronous Control Units , 1982, IEEE Transactions on Computers.

[71]  Alexandre Yakovlev,et al.  Visualization and resolution of coding conflicts in asynchronous circuit design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[72]  Jordi Cortadella,et al.  Structural methods for the synthesis of speed-independent circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[73]  Victor Varshavsky,et al.  Asynchronous Control Device Design by Net Model Behavior Simulation , 1996, Application and Theory of Petri Nets.

[74]  Hemangee K. Kapoor,et al.  Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis , 2004, Proceedings. 41st Design Automation Conference, 2004..

[75]  A. YakovlevyDpt.  Design and Evaluation of Two Asynchronous Token Ring Adapters , 1996 .

[76]  Alexander Schrijver,et al.  Theory of linear and integer programming , 1986, Wiley-Interscience series in discrete mathematics and optimization.