Multi-bit continuous-time delta-sigma modulator for audio application

The design considerations for low-power continuous time (CT) delta-sigma (ΔΣ) modulators is studied and circuit design details for a 13.5 bit modulator are given. The converter has been designed in a 0.5 um C5FN AMI CMOS technology and achieves a maximum signal-to-noise ratio (SNR) of 85 dB in a 48 kHz bandwidth and dissipates 5.4 mW from a 5 V supply when clocked at 6.144 MHz. It features a third-order active-RC loop filter, a 4-bit flash quantizer along with a Data Weighted averaging (DWA). The loop filter architecture and its coefficients have been targeted for the minimum power dissipation. The DWA also has been implemented by standard cell based synthesis to further optimize power. The figure of merit (FoM) of the CT-ΔΣ modulator is 3.71 pJ/bit. The fabricated chip of the modulator occupies an area of 4.5 mm2.

[1]  Shanthi Pavan,et al.  A power efficient continuous time ΔΣ modulator with 15 MHz bandwidth and 70 dB dynamic range , 2010 .

[2]  R. Schreier,et al.  Delta-sigma data converters : theory, design, and simulation , 1997 .

[3]  R. Baird,et al.  Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging , 1995 .

[4]  K. Reddy,et al.  A 20.7mW continuous-time ΔΣ modulator with 15MHz bandwidth and 70 dB dynamic range , 2008, ESSCIRC 2008 - 34th European Solid-State Circuits Conference.

[5]  B. Leung,et al.  Multibit Sigma - Delta A/D converter incorporating a novel class of dynamic element matching techniques , 1992 .

[6]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ modulator with 67dB dynamic range in 10MHz bandwidth , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  R. T. Baird,et al.  Linearity enhancement of multibit delta-sigma A/D and D/A converters using data weighted averaging , 1995 .

[8]  Maurits Ortmanns,et al.  Continuous time sigma-delta A/D conversion : fundamentals, performance limits and robust implementations , 2006 .

[9]  I. Fujimori,et al.  A 90 dB SNR, 2.5 MHz output rate ADC using cascaded multibit /spl Delta//spl Sigma/ modulation at 8x oversampling ratio , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[10]  James C. CAhY.  A Use of Double Integration in Sigma Delta Modulation , 1985 .

[11]  Shanthi Pavan,et al.  A Power Optimized Continuous-Time $\Delta \Sigma $ ADC for Audio Applications , 2008, IEEE Journal of Solid-State Circuits.

[12]  C. Holuigue,et al.  A 20-mW 640-MHz CMOS Continuous-Time $\Sigma\Delta$ ADC With 20-MHz Signal Bandwidth, 80-dB Dynamic Range and 12-bit ENOB , 2006, IEEE Journal of Solid-State Circuits.

[13]  L. Longo,et al.  A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibit delta-sigma modulation at 8/spl times/ oversampling ratio , 2000, IEEE Journal of Solid-State Circuits.

[14]  Gabor C. Temes,et al.  Oversampling delta-sigma data converters : theory, design, and simulation , 1992 .

[15]  L.J. Breems,et al.  A cascaded continuous-time /spl Sigma//spl Delta/ Modulator with 67-dB dynamic range in 10-MHz bandwidth , 2004, IEEE Journal of Solid-State Circuits.

[16]  Gabor C. Temes,et al.  Understanding Delta-Sigma Data Converters , 2004 .

[17]  Shanthi Pavan,et al.  Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique , 2010, IEEE Journal of Solid-State Circuits.

[18]  R. Schreier,et al.  Mismatch shaping for a current-mode multibit delta-sigma DAC , 1999, IEEE J. Solid State Circuits.

[19]  Feng Chen,et al.  A High Resolution Multibit Sigma-delta Modulator With Individual Level Averaging , 1994, Proceedings of 1994 IEEE Symposium on VLSI Circuits.

[20]  Gabor C. Temes,et al.  Oversampling Delta Sigma Data Converters , 1991 .

[21]  L. R. Carley,et al.  A noise-shaping coder topology for 15+ bit converters , 1989 .

[22]  M. Clara,et al.  A 70-mW 300-MHz CMOS continuous-time /spl Sigma//spl Delta/ ADC with 15-MHz bandwidth and 11 bits of resolution , 2004, IEEE Journal of Solid-State Circuits.

[23]  John G. Kenney,et al.  Design of multibit noise-shaping data converters , 1993 .