A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits
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[1] SUDHAKAR M. REDDY,et al. Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.
[2] Hideo Fujiwara. On Closedness and Test Complexity of Logic Circuits , 1981, IEEE Transactions on Computers.
[3] Mark G. Karpovsky,et al. Fault Detection in Combinational Networks by Reed-Muller Transforms , 1989, IEEE Trans. Computers.
[4] Wilfried Daehn,et al. A Hardware Approach to Self-Testing of Large Programmable Logic Arrays , 1981, IEEE Transactions on Computers.
[5] Marek Perkowski,et al. Design For Testability Properties of AND/XOR Networks , 1993 .
[6] Nur A. Touba,et al. BETSY: synthesizing circuits for a specified BIST environment , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[7] Marek Perkowski,et al. Algorithm for the generation of disjoint cubes for completely and incompletely specified boolean functions , 1991 .
[8] Lech Józwiak,et al. Term Trees in Application to an Effective and Efficient ATPG for AND-EXOR and AND-OR Circuits , 2002, VLSI Design.
[9] Fabrizio Lombardi,et al. Testing and diagnosis of VLSI and ULSI , 1988 .
[10] Sudhakar M. Reddy,et al. Fault Detection and Design For Testability of CMOS Logic Circuits , 1988 .
[11] Tsutomu Sasao. Easily testable realizations for generalized Reed-Muller expressions , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).
[12] J. Saul,et al. Two-level logic circuits using EXOR sums of products , 1993 .
[13] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[14] J. Max Cortner. Digital Test Engineering , 1987 .
[15] Sudhakar M. Reddy,et al. Fault Detecting Test Sets for Reed-Muller Canonic Networks , 1975, IEEE Transactions on Computers.
[16] A. K. Choudhury,et al. Testable design of RMC networks with universal tests for detecting stuck-at and bridging faults , 1985 .
[17] Tsutomu Sasao,et al. Logic Synthesis and Optimization , 1997 .
[18] 藤原 秀雄,et al. Logic testing and design for testability , 1985 .
[19] B. Koenemann,et al. Built-in logic block observation techniques , 1979 .
[20] Kolar L. Kodandapani. A Note on Easily Testable Realizations for Logic Functions , 1974, IEEE Transactions on Computers.
[21] John P. Hayes. On Modifying Logic Networks to Improve Their Diagnosability , 1974, IEEE Transactions on Computers.
[22] Jacob Savir,et al. Built In Test for VLSI: Pseudorandom Techniques , 1987 .
[23] Edward J. McCluskey,et al. Circuits for pseudoexhaustive test pattern generation , 1986, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[24] Marek A. Perkowski,et al. Minimization of exclusive sum-of-products expressions for multiple-valued input, incompletely specified functions , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[25] Rolf Drechsler,et al. Testability of 2-Level AND/EXOR Circuits , 1999, J. Electron. Test..
[26] Dhiraj K. Pradhan,et al. Universal Test Sets for Multiple Fault Detection in AND-EXOR Arrays , 1978, IEEE Transactions on Computers.
[27] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .