Concurrent design analysis of A 8500V ESD-protected SP10T switch in SOI CMOS

SPMT-ESD interaction and co-design analysis are critical to designing SPMT with high ESD protection. New co-design approach helps to deliver a high linearity SP10T with 8500V ESD protection in SOI CMOS, compared favorable to the state-of-the-art with 0-700V ESD protections [1-3].