Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme

This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom carry-save-arithmetic (CSA) datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a uniformity transformation imposed on the basic architectures of CSA multipliers and CSA chain-adders/subtractors. The design flow for the implementation of the core is analyzed in detail, and a novel reconfigurable architecture prototype is presented. The paper concludes with the experimental results showing that our architecture performs an average latency reduction of 32.63%, compared with datapaths of primitive computational resources, with a tolerable overhead in hardware utilization.

[1]  Tsutomu Sasao,et al.  Input Variable Assignment and Output Phase Optimization of PLA's , 1984, IEEE Transactions on Computers.

[2]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[3]  Spyros Tragoudas,et al.  A high-performance data path for synthesizing DSP kernels , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Wei Zhao,et al.  Synthesis of reusable DSP cores based on multiple behaviors , 1996, Proceedings of International Conference on Computer Aided Design.

[5]  Sebastian Wallner.  A configurable system-on-chip architecture for embedded and real-time applications: concepts, design and realization , 2005, J. Syst. Archit..

[6]  Michael A. Schuette,et al.  Morphable Multipliers , 2002, FPL.

[7]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[8]  Kaushik Roy,et al.  Synthesis of application-specific highly efficient multi-mode cores for embedded systems , 2005, TECS.

[9]  Scott Hauck,et al.  Reconfigurable computing: a survey of systems and software , 2002, CSUR.

[10]  Miodrag Potkonjak,et al.  Performance optimization using template mapping for datapath-intensive high-level synthesis , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  T. Arslan,et al.  An AMBA AHB-based reconfigurable SoC architecture using multiplicity of dedicated flyby DMA blocks , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[12]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[13]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[14]  Scott Hauck,et al.  The Chimaera reconfigurable functional unit , 1997, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[15]  Fadi J. Kurdahi,et al.  Design and Implementation of the MorphoSys Reconfigurable Computing Processor , 2000, J. VLSI Signal Process..

[16]  Nikil D. Dutt,et al.  Using global code motions to improve the quality of results for high-level synthesis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.