An Improved VLSI Architecture of S-box for AES Encryption

This paper presents an improved VLSI architecture of S-box for AES encryption system. Certain basic blocks in conventional architecture are replaced by efficient multiplexers and an optimized combinational logic to facilitate speed improvement. The proposed as well as conventional architecture are implemented in Xilinx FPGA and 0.18 μm standard cell ASIC technology. ASIC implementation indicates speed enhancement while maintaining constant area compared to conventional architecture. FPGA implementation also confirms speed improvement of about 0.6 ns along with low utilization of FPGA fabrics. Furthermore, there is significant power improvement (155 %) compared to conventional structure.

[1]  Warsuzarina Mat Jubadi,et al.  Design of AES S-box using combinational logic optimization , 2010, 2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA).

[2]  Keshab K. Parhi,et al.  High-speed VLSI architectures for the AES algorithm , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  José G. Delgado-Frias,et al.  FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm , 2010, J. Syst. Archit..

[4]  Miguel A. Vega-Rodríguez,et al.  A new methodology to implement the AES algorithm using partial and dynamic reconfiguration , 2010, Integr..

[5]  William Stallings,et al.  Cryptography and network security (2nd ed.): principles and practice , 1998 .

[6]  Ishak Aris,et al.  Design of an ultra high speed AES processor for next generation IT security , 2011, Comput. Electr. Eng..

[7]  Cheng-Wen Wu,et al.  A high-throughput low-cost AES processor , 2003, IEEE Communications Magazine.

[8]  Arash Reyhani-Masoleh,et al.  A Lightweight High-Performance Fault Detection Scheme for the Advanced Encryption Standard Using Composite Fields , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[9]  Behrouz A. Forouzan,et al.  Cryptography and network security , 1998 .

[10]  Kamal El-Sankary,et al.  High-Speed AES Encryptor With Efficient Merging Techniques , 2010, IEEE Embedded Systems Letters.

[11]  S. M. Rezaul Hasan,et al.  Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate , 2013, Integr..

[12]  Mostafa I. Soliman,et al.  FPGA implementation and performance evaluation of a high throughput crypto coprocessor , 2011, J. Parallel Distributed Comput..

[13]  Edwin NC Mui,et al.  Practical Implementation of Rijndael S-Box Using Combinational Logic , 2007 .