论文信息 - 14-bit CMOS pipeline ADC with dual-calibration

14-bit CMOS pipeline ADC with dual-calibration

A new way of designing a 14-bit pipeline analogue-to-digital converter is described. Combined gain calibration and capacitor mismatch correction permit limiting power consumption and achieve a differential nonlinearity of 0.25LSB in a low-cost digital CMOS process (0.18 µm).

Patrice Gamand | C. Erdmann | S. Dumont | P. Gandy

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