SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs

2.5D stacking technology allows us to build high performance and high capacity FPGA devices at reasonable costs. The communication between multiple dies happen on a passive silicon interposer at high speed, which pose several interesting challenges. Due to clock skew characteristics across multiple dies and increase in the min-max spread of delays, place-and-route tools need to address inter-die hold violations and optimize for performance. We implement a tractable SAT based methodology to achieve this by minimally detouring data paths to meet all hold requirements while optimizing performance. We also confine the solution to a small window around each inter-die (Laguna) channel to reduce routing resource utilization, congestion, and scale the methodology to any Laguna channel utilization. We improve performance across the interface by 11% compared to a state-of-the-art commercial flow and meet a 500MHz spec on Xilinx(R) UltraScale+(TM) devices in 2E speedgrade. We address the scalability concerns of SAT and show how we can use this in practice with negligible runtimes in implementation tools. Our solution paves the way for FPGA-as-a-service platforms where fast inter-die communication, that does not interfere with user specific logic, is pivotal to their success.

[1]  Sharad Malik,et al.  Efficient conflict driven learning in a Boolean satisfiability solver , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[2]  Miroslav N. Velev,et al.  Comparison of Boolean Satisfiability Encodings on FPGA Detailed Routing Problems , 2008, 2008 Design, Automation and Test in Europe.

[3]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[4]  Abhishek Joshi,et al.  Boolean Satisfiability-Based Routing and Its Application to Xilinx UltraScale Clock Network , 2016, FPGA.

[5]  Rob A. Rutenbar,et al.  FPGA routing and routability estimation via Boolean satisfiability , 1997, FPGA '97.

[6]  Joong-Ho Kim,et al.  Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[7]  K. Saban Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity , Bandwidth , and Power Efficiency , 2009 .

[8]  Rob A. Rutenbar,et al.  A New FPGA Detailed Routing Approach Via , 2002 .

[9]  R. Chaware,et al.  Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[10]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Shyamapada Mukherjee,et al.  SAT based solutions for detailed routing of island style FPGA architectures , 2015, Microelectron. J..

[12]  Patrick Dorsey Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency , 2010 .

[13]  J. P. Marques,et al.  GRASP : A Search Algorithm for Propositional Satisfiability , 1999 .

[14]  Niklas Sörensson,et al.  An Extensible SAT-solver , 2003, SAT.

[15]  Henri Fraisse,et al.  A SAT-based Timing Driven Place and Route Flow for Critical Soft IP , 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

[16]  Rob A. Rutenbar,et al.  A comparative study of two Boolean formulations of FPGA detailed routing constraints , 2001, IEEE Transactions on Computers.