Design of an ultra-low power SA-ADC with medium/high resolution and speed

Design strategies for power effective medium/high resolution Successive-Approximation ADC are discussed. The study considers reducing the power of the capacitive array with suitable capacitive attenuators that do not need using non-unity capacitors. The design of minimum power comparators is analyzed and a novel comparator scheme, named time-domain comparator, is described. The proposed methodologies, verified with a test design, is capable to provide 12-bit with 50-kHz signal band and 1-V supply. The achieved FoM is 14 fj/conv-level, which is well below the state-of-the-art.

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