论文信息 - Vertical nanowire transistor-based CMOS: VTC analysis

Vertical nanowire transistor-based CMOS: VTC analysis

In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.

B. Anand | S. K. Manhas | Satish Maheshwaram

[1] N. Singh,et al. High-Performance Poly-Si Vertical Nanowire Thin-Film Transistor and the Inverter Demonstration , 2011, IEEE Electron Device Letters.

[2] N. Singh,et al. Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS , 2011, IEEE Electron Device Letters.

[3] Dim-Lee Kwong,et al. Si-nanowire CMOS inverter logic fabricated using gate-all-around (GAA) devices and top-down approach , 2008 .

[4] B. Anand,et al. Device Circuit Co-Design Issues in Vertical Nanowire CMOS Platform , 2012, IEEE Electron Device Letters.

[5] Bulusu Anand,et al. Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis , 2013, IEEE Transactions on Electron Devices.

[6] N. Singh,et al. Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φm and VT tune-ability , 2008, 2008 IEEE International Electron Devices Meeting.

[7] Sangsig Kim,et al. Top-down fabrication of fully CMOS-compatible silicon nanowire arrays and their integration into CMOS Inverters on plastic. , 2011, ACS nano.