Arithmetic formats for implementing artificial neural networks on FPGAs
暂无分享,去创建一个
[1] Scott McMillan,et al. A re-evaluation of the practicality of floating-point operations on FPGAs , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).
[2] Wolfgang J. Paul,et al. On the design of IEEE compliant floating point units , 1997, Proceedings 13th IEEE Sympsoium on Computer Arithmetic.
[3] G. Kane. Parallel Distributed Processing: Explorations in the Microstructure of Cognition, vol 1: Foundations, vol 2: Psychological and Biological Models , 1994 .
[4] André DeHon,et al. The Density Advantage of Configurable Computing , 2000, Computer.
[5] Guido D. Salvucci,et al. Ieee standard for binary floating-point arithmetic , 1985 .
[6] J. L. Holt,et al. Back propagation simulations using limited precision calculations , 1991, IJCNN-91-Seattle International Joint Conference on Neural Networks.
[7] James L. McClelland,et al. Parallel distributed processing: explorations in the microstructure of cognition, vol. 1: foundations , 1986 .
[8] P. Belanovic. Library of Parameterized Hardware Modules for Floating-Point Arithmetic with An Example Application , 2002 .
[9] S. Hyakin,et al. Neural Networks: A Comprehensive Foundation , 1994 .