A new approach to evaluating internal Xilinx FPGA resources

Abstract In this paper, a new approach of application test process is presented aimed at verifying internal Xilinx FPGA (field programmable gate array) resources using a multi-load bitstream system. Basically, the new system comprises an algorithmic part, running on a PC (the software aspect), and an ad hoc hardware architecture. The bitstreams necessary for testing FPGA internal resources are automatically generated on a PC using a sequential algorithm, which varies according to the FPGA chip to be evaluated, and are subsequently downloaded onto the hardware architecture. Next, a customized application, also run on a PC, downloads the previously generated bitstreams consecutively, using the Xilinx Impact tool. The hardware architecture comprises two boards based on FPGAs. The first, called the Mother Board (MB) is used to implement the design which is responsible for sending and receiving the tests to and from the second board, called the FUT (FPGA under test) Board, where the FPGA to be tested is located and where the evaluation test is conducted. Thus, in order to ensure correct transmission of the test/results patterns, a communication bus between both boards is required. The two FPGAs are configured using JTAG protocol, and reconfiguration of both is carried out via a multi-load algorithm which, once each resource unit has been tested, downloads a new bitstream onto the FUT. The present proposal enables the resources of an FPGA to be tested and provides an exhaustive, complete report on the status of the FPGAs different internal resources, with a view to reusing the FPGA for another application.

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