Defect Detection Rate through IDDQ for Production Testing

With the miniaturization of the diffusion process, the leak current per transistor tends to increase and the number of transistors per die tends to become larger, thus rendering more difficult the discrimination through the absolute value of IDDQ (quiescent power supply current) that is required to detect defects on VLSI (Very Large Scale Integration). While various statistical methods have been disclosed, this paper describes first the effects of an increase in the average value of IDDQ due to process dispersion on the IDDQ distribution and presents a theorization to estimate the defect detection rate of various IDDQ testing methods. Corroborative results will then show the validity of the presented theory on the defect detection rate of IDDQ.

[1]  Takayasu Sakurai,et al.  Optimum Device Consideration for Standby Power Reduction Scheme Using Drain-Induced Barrier Lowering , 2003 .

[2]  Vishwani D. Agrawal,et al.  Graphical $I_{\rm DDQ}$ Signatures Reduce Defect Level and Yield Loss , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Takayasu Sakurai 2004 Digital -- Advanced Solid State Circuits Forum: "Managing Variability in sub-100nm Designs" Adaptive Circuit Techniques for Managing Variations , 2004 .

[4]  Vishwani D. Agrawal,et al.  Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits [Book Review] , 2000, IEEE Circuits and Devices Magazine.

[5]  J. Hirase,et al.  The effect of fault detection by IDDq measurement for CMOS VLSIs , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[6]  Takayasu Sakurai,et al.  A simple MOSFET model for circuit analysis , 1991 .

[7]  Claude Thibeault An histogram based procedure for current testing of active defects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[8]  R. Keith Treece,et al.  CMOS IC stuck-open-fault electrical effects and design considerations , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[9]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production IDDQ testing , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[10]  Vishwani D. Agrawal,et al.  New graphical I/sub DDQ/ signatures reduce defect level and yield loss , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[11]  Yoshiyuki Tanaka,et al.  IDDQ Testing Method using a Scan Pattern for Production Testing , 2005, 14th Asian Test Symposium (ATS'05).

[12]  Yukio Okuda DECOUPLE: defect current detection in deep submicron I/sub DDQ/ , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[13]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production I/sub DDQ/ testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).