Challenges in Cell-Aware Test

Physical defects like opens and bridging defects can occur during the fabrication process of integrated circuits. The logic level abstraction of these physical defects, named fault models like stuck-at, transition, bridge, and small-delay defect, have been proposed, and are widely used in the industry for Automatic Test Pattern Generation (ATPG). However, as the technology moves to increasingly smaller geometries, these fault models and their associated test patterns are becoming less effective. The reason behind this is that existing fault models only consider faults on cell inputs and outputs, plus the interconnects between them. A growing number of defects occur within the cells, which are not explicitly targeted by traditional ATPG. N-detect algorithms can potentially test such defects by generating multiple patterns which detect cell-internal defects randomly. Cell-Aware Test (CAT) tries to solve this problem by uniquely targeting every possible internal defect. This is done via a series of analog simulations of all possible input combinations for all identified possible defects, which come at a significant runtime penalty. This paper shows a comparison of the static and transition patterns that are generated by the CAT methodology and the traditional ATPG for different library and cell parameters. This paper also aims to throw light on the quality concerns of the generated User Defined Fault Model (UDFM) by comparing results while varying different parameters of analog simulations, which reflect the variation due to Process, Voltage and Temperature (PVT). The increase in performance, pattern count and test coverage with respect to two Arm designs is also presented, which reflects the actual cost and gains of the CAT model over traditional ATPG.