On the generation of pseudo-deterministic two-patterns test sequence with LFSRs

Many Built-in Self Test (BIST) pattern generators use Linear Feedback Shift Registers (LFSR) to generate test sequences. In this paper, we address the generation of deterministic pairs of patterns for delay faults testing with LFSRs. A new synthesis procedure for a n-size LFSR is given and guarantees that a deterministic set of n precomputed test pairs is embedded in the maximal length pseudo-random test sequence of the LFSR. Sufficient and necessary conditions for the synthesis of this pseudo-deterministic LFSR are provided and show that at-speed delay faults testing becomes a reality without any additional cost for the LFSR. Moreover, since the theoretical properties of LFSRs are preserved, our method could be beneficially used in conjunction with any other technique proposed so far.

[1]  Thomas W. Williams,et al.  Design for Testability - A Survey , 1982, IEEE Trans. Computers.

[2]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[3]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Bernard Courtois,et al.  Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers , 1992 .

[5]  Karl Fuchs,et al.  A new BIST approach for delay fault testing , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  Edward J. McCluskey,et al.  TWO-PATTERN TEST CAPABILITIES OF AUTONOMOUS TPG CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[7]  Dhiraj K. Pradhan,et al.  Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa , 1996, IEEE Trans. Computers.

[8]  Janusz Rajski,et al.  Constructive multi-phase test point insertion for scan-based BIST , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[9]  Charles R. Kime,et al.  Pseudo-Exhaustive Adjacency Testing: A BIST Approach for Stuck-Open Faults , 1985, International Test Conference.

[10]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[11]  Wilfried Daehn,et al.  Hardware Test Pattern Generation for Built-In Testing , 1981, International Test Conference.

[12]  Karl Fuchs,et al.  A BIST approach to delay fault testing with reduced test length , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[13]  Nur A. Touba,et al.  Transformed pseudo-random patterns for BIST , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[14]  Kiyoshi Furuya,et al.  Evaluations of various TPG circuits for use in two-pattern testing , 1994, Proceedings of IEEE 3rd Asian Test Symposium (ATS).

[15]  Christian Dufaza,et al.  BIST hardware generator for mixed test scheme , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[16]  Constantin Halatsis,et al.  Accumulator-based BIST approach for stuck-open and delay fault testing , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[17]  Melvin A. Breuer,et al.  Test embedding with discrete logarithms , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Sandeep K. Gupta,et al.  BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms , 1996, IEEE Trans. Computers.

[19]  Dhiraj K. Pradhan,et al.  GLFSR-a new test pattern generator for built-in-self-test , 1994, Proceedings., International Test Conference.

[20]  Yervant Zorian,et al.  Built-in self-test for digital integrated circuits , 1994, AT&T Technical Journal.

[21]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[22]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[23]  Sandeep K. Gupta,et al.  BIST test pattern generators for stuck-open and delay testing , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[24]  Spyros Tragoudas,et al.  Generating deterministic unordered test patterns with counters , 1996, Proceedings of 14th VLSI Test Symposium.

[25]  D. Michael Miller,et al.  BIST generators for sequential faults , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[26]  Corot W. Starke,et al.  Built-In Test for CMOS Circuits , 1984, ITC.

[27]  Slawomir Pilarski,et al.  BIST and delay fault detection , 1993, Proceedings of IEEE International Test Conference - (ITC).

[28]  Dhiraj K. Pradhan,et al.  A novel pattern generator for near-perfect fault-coverage , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[29]  Sandeep K. Gupta,et al.  Weighted random robust path delay testing of synthesized multilevel circuits , 1994, Proceedings of IEEE VLSI Test Symposium.