WTPGA: a novel weighted test-pattern generation approach for VLSI built-in self test

A weighted test-pattern generation approach (WTPGA) is reported and applied to two very well known circuits. WTPGA was applied specifically to a 4-bit ALU (arithmetic logic unit) and a minimal set of test patterns with very high fault coverage resulted. It has been observed that there exists a correlation between the rate of the circuit switching activity on application of the test-patterns and the increase in fault coverage. WTPGA also takes advantage of functional test patterns in computation of the signal probabilities and it is known that good functional test sets fully exercise the circuit. It is also implied that the technique described can be applied in developing a minimal set of pseudorandom patterns, generated internal to the device for built-in self-test.<<ETX>>