Monolithic 3-D FPGAs This paper investigates the application of 2.5-D and 3-D integrated circuits as a medium for implementing reconfigurable systems.
暂无分享,去创建一个
[1] X. Garros,et al. New insights on bottom layer thermal stability and laser annealing promises for high performance 3D VLSI , 2014, 2014 IEEE International Electron Devices Meeting.
[2] J. Mazurier,et al. Advances, challenges and opportunities in 3D CMOS sequential integration , 2011, 2011 International Electron Devices Meeting.
[3] Arifur Rahman,et al. System-level performance evaluation of three-dimensional integrated circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[4] Weidong Xu,et al. Rothko: A Three-Dimensional FPGA , 1998, IEEE Des. Test Comput..
[5] N. Sakimura,et al. Polymer solid-electrolyte (PSE) switch embedded in 90nm CMOS with forming-free and 10nsec programming for low power, nonvolatile programmable logic (NPL) , 2010, 2010 International Electron Devices Meeting.
[6] Abbas El Gamal,et al. Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory , 2012, 2012 IEEE International Solid-State Circuits Conference.
[7] Wei Wang,et al. rFGA: CMOS-nano hybrid FPGA using RRAM components , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.
[8] S. Ikeda,et al. A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor , 2008, 2008 IEEE International Electron Devices Meeting.
[9] O. Richard,et al. 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation , 2011, 2011 International Electron Devices Meeting.
[10] A. Chin,et al. Three-dimensional metal gate-high-/spl kappa/-GOI CMOSFETs on 1-poly-6-metal 0.18-/spl mu/m Si devices , 2005, IEEE Electron Device Letters.
[11] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[12] R. Fabian Pease,et al. Low-Temperature Monolithic Three-Layer 3-D Process for FPGA , 2013, IEEE Electron Device Letters.
[13] T. Sakamoto,et al. A nonvolatile programmable solid-electrolyte nanometer switch , 2004, IEEE Journal of Solid-State Circuits.
[14] Ogun Turkyilmaz,et al. RRAM-based FPGA for "Normally Off, Instantly On" applications , 2014, J. Parallel Distributed Comput..
[15] Abbas El Gamal,et al. The prospect of 3D-IC , 2009, 2009 IEEE Custom Integrated Circuits Conference.
[16] H.J. De Los Santos,et al. RF MEMS for ubiquitous wireless connectivity. Part II. Application , 2004, IEEE Microwave Magazine.
[17] Tony F. Wu,et al. Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs , 2014, 2014 IEEE International Electron Devices Meeting.
[18] H.-S. Philip Wong,et al. Efficient FPGAs using nanoelectromechanical relays , 2010, FPGA '10.
[19] James Ball. Designing Soft-Core Processors for FPGAs , 2007 .
[20] Peide D. Ye,et al. First experimental demonstration of Ge CMOS circuits , 2014, 2014 IEEE International Electron Devices Meeting.
[21] Masato Motomura,et al. Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS , 2011, 2011 IEEE International Solid-State Circuits Conference.
[22] André DeHon,et al. Impact of Memory Architecture on FPGA Energy Consumption , 2015, FPGA.
[23] H. Wong,et al. Forming-free nitrogen-doped AlOX RRAM with sub-μA programming current , 2011, 2011 Symposium on VLSI Technology - Digest of Technical Papers.
[24] Kikuo Ono,et al. An LCD addressed by a-Si:H TFTs with peripheral poly-Si TFT circuits , 1993, Proceedings of IEEE International Electron Devices Meeting.
[25] Hiroyuki Mizuno,et al. Green Computing with Emerging Memory , 2013 .
[26] H. Grampeix,et al. Enabling 3D Monolithic Integration , 2008 .
[27] Sung Kyu Lim,et al. Power-performance study of block-level monolithic 3D-ICs considering inter-tier performance variations , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[28] M. Takata,et al. Nonvolatile SRAM based on Phase Change , 2006, 2006 21st IEEE Non-Volatile Semiconductor Memory Workshop.
[29] Subhasish Mitra,et al. Monolithic three-dimensional integration of carbon nanotube FETs with silicon CMOS , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
[30] Shoji Ikeda,et al. Fabrication of a magnetic tunnel junction-based 240-tile nonvolatile field-programmable gate array chip skipping wasted write operations for greedy power-reduced logic applications , 2013, IEICE Electron. Express.
[31] N. Shimomura,et al. Impact of ultra low power and fast write operation of advanced perpendicular MTJ on power reduction for high-performance mobile CPU , 2012, 2012 International Electron Devices Meeting.
[32] Daisuke Suzuki,et al. Fabrication of a nonvolatile lookup-table circuit chip using magneto/semiconductor-hybrid structure for an immediate-power-up field programmable gate array , 2009, 2009 Symposium on VLSI Circuits.
[33] Russell Tessier,et al. FPGA Architecture: Survey and Challenges , 2008, Found. Trends Electron. Des. Autom..
[34] S. Wong,et al. Monolithic 3D Integrated Circuits , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
[35] C. S. Chen,et al. Characterization and simulation of NMOS pass transistor reliability for FPGA routing circuits , 2013, 2013 IEEE International Conference on Microelectronic Test Structures (ICMTS).
[36] Shoji Ikeda,et al. High-density and low-power nonvolatile static random access memory using spin-transfer-torque magnetic tunnel junction , 2012 .
[37] R. Howe,et al. Design Considerations for Complementary Nanoelectromechanical Logic Gates , 2007, 2007 IEEE International Electron Devices Meeting.
[38] Hai Wei,et al. Monolithic three-dimensional integration of carbon nanotube FET complementary logic circuits , 2013, 2013 IEEE International Electron Devices Meeting.
[39] Roger Fabian W. Pease,et al. Semiconductor crystal islands for three-dimensional integration , 2010 .
[40] Fabien Clermidy,et al. A CBRAM-based compact interconnect switch for non-volatile reconfigurable logic circuits , 2013, Proceedings of 2013 International Conference on IC Design & Technology (ICICDT).
[41] S. Lai,et al. Non-volatile memory technologies: The quest for ever lower cost , 2008, 2008 IEEE International Electron Devices Meeting.
[42] Arif Rahman. Recent advances in die stacking and 3D FPGA , 2013, FPT.
[43] Shuu'ichirou Yamamoto,et al. Nonvolatile Static Random Access Memory Using Magnetic Tunnel Junctions with Current-Induced Magnetization Switching Architecture , 2009 .
[44] José G. Delgado-Frias,et al. CNTFET 8T SRAM cell performance with near-threshold power supply scaling , 2013, 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013).
[45] Kaustav Banerjee,et al. Performance analysis and technology of 3-D ICs , 2000, SLIP '00.
[46] Mingjie Lin,et al. Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[47] Jacques-Olivier Klein,et al. High Density Asynchronous LUT Based on Non-volatile MRAM Technology , 2010, 2010 International Conference on Field Programmable Logic and Applications.
[48] Vladimir Stojanovic,et al. Integrated circuit design with NEM relays , 2008, ICCAD 2008.
[49] G. De Micheli,et al. Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs , 2013, IEEE Transactions on Nanotechnology.
[50] Jan M. Rabaey,et al. Low-Energy FPGAs - Architecture and Design , 2001 .
[51] James Myers,et al. Device and technology implications of the Internet of Things , 2014, 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers.
[52] Jason Cong,et al. FPGA-RPI: A Novel FPGA Architecture With RRAM-Based Programmable Interconnects , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[53] P. Griffin,et al. Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate , 2006, IEEE Electron Device Letters.
[54] Shimeng Yu,et al. Metal–Oxide RRAM , 2012, Proceedings of the IEEE.
[55] Lionel Torres,et al. Magnetic tunnelling junction based FPGA , 2006, FPGA '06.
[56] Mingjie Lin,et al. A routing fabric for monolithically stacked 3D-FPGA , 2007, FPGA '07.
[57] Anantha Chandrakasan,et al. Wiring requirement and three-dimensional integration technology for field programmable gate arrays , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[58] H.-S. Philip Wong,et al. Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[59] Sung Kyu Lim,et al. Fast and accurate thermal modeling and optimization for monolithic 3D ICs , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).
[60] N. Banno,et al. First demonstration of logic mapping on nonvolatile programmable cell using complementary atom switch , 2012, 2012 International Electron Devices Meeting.
[61] Byung-Il Ryu,et al. Highly area efficient and cost effective double stacked S/sup 3/ (stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[62] Zheng Wang,et al. Nonvolatile SRAM Cell , 2006, 2006 International Electron Devices Meeting.
[63] Vladimir Stojanovic,et al. Demonstration of integrated micro-electro-mechanical switch circuits for VLSI applications , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).
[64] Kaustav Banerjee,et al. 3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration , 2001, Proc. IEEE.
[65] Wei Wang,et al. FPGA Based on Integration of CMOS and RRAM , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[66] Yusuke Shuto,et al. Nonvolatile Power-Gating Field-Programmable Gate Array Using Nonvolatile Static Random Access Memory and Nonvolatile Flip-Flops Based on Pseudo-Spin-Transistor Architecture with Spin-Transfer-Torque Magnetic Tunnel Junctions , 2012 .
[67] Vaughn Betz,et al. VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.
[68] J. Xie,et al. Wafer-level vacuum sealing and encapsulation for fabrication of CMOS MEMS thermoelectric power generators , 2010, 2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems (MEMS).
[69] Tetsuo Endoh,et al. Design of a Compact Nonvolatile Four-Input Logic Element Using a Magnetic Tunnel Junction and Metal-Oxide-Semiconductor Hybrid Structure , 2012 .
[70] Daisuke Suzuki,et al. Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA , 2009 .
[71] H. Noguchi,et al. Progress of STT-MRAM technology and the effect on normally-off computing systems , 2012, 2012 International Electron Devices Meeting.
[72] Meng-Fan Chang,et al. Low Store Energy, Low VDDmin, 8T2R Nonvolatile Latch and SRAM With Vertical-Stacked Resistive Memory (Memristor) Devices for Low Power Mobile Applications , 2012, IEEE Journal of Solid-State Circuits.
[73] M. Hosomi,et al. A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..