Silicon nanotechnologies and emerging non-silicon nanoelectronics
暂无分享,去创建一个
[1] R. Chau,et al. Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.
[2] M. Ieong,et al. Investigation of FinFET Devices for 32nm Technologies and Beyond , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[3] G. Dewey,et al. Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[4] High Performance Carbon Nanotube Ring Oscillator , 2006, 2006 64th Device Research Conference.
[5] Robert S. Chau. Advanced Metal Gate/High-K Dielectric Stacks for High-Performance CMOS Transistors , 2004 .
[6] S. Tyagi,et al. High performance 35nm L/sub GATE/ CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2nm gate oxide , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[7] R. Chau,et al. Opportunities and challenges of III-V nanoelectronics for future high-speed, low-power logic applications , 2005, IEEE Compound Semiconductor Integrated Circuit Symposium, 2005. CSIC '05..
[8] R. Chau,et al. 85nm gate length enhancement and depletion mode InSb quantum well transistors for ultra high speed and very low power digital logic applications , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[9] J. Kavalieros,et al. High-/spl kappa//metal-gate stack and its MOSFET characteristics , 2004, IEEE Electron Device Letters.
[10] Suman Datta,et al. High- /Metal-Gate Stack and Its MOSFET Characteristics , 2004 .
[11] J. Kavalieros,et al. A 50 nm depleted-substrate CMOS transistor (DST) , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).
[12] R. Chau,et al. A 90-nm logic technology featuring strained-silicon , 2004, IEEE Transactions on Electron Devices.
[13] P. Bai,et al. A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[14] S. Datta,et al. Novel InSb-based quantum well transistors for ultra-high speed, low power logic applications , 2004, Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004..