An area-saving decoder structure for ROMs

Read-only memories (ROMs) are widely used in both digital communication systems and daily consumer electronics. The major functions of ROMs are storage of data, programs, firmwares, etc. In this paper, a three-dimensional decoding structure for ROMs is proposed. The number of address decoding stages is drastically shortened. Hence, the delay is reduced, as well as the power consumption and area. The analysis of overall transistor count and delay is thoroughly derived. A real 256 /spl times/ 8 ROM possessing the proposed decoder is physically fabricated by 0.5-/spl mu/m two-poly two-metal (2P2M) CMOS technology.

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