PAPER Special Section on Fundamentals and Applications of Advanced Semiconductor Devices Design and Simulation of Asymmetric MOSFETs
暂无分享,去创建一个
SUMMARY A novel asymmetric MOSFET with no LDD on the source side is simulated on bulk-Si using a device simulator (SILVACO). In order to overcome the problems of the conventional asymmetric process, a novel asymmetric MOSFET using mesa structure and sidewall spacer gate is proposed which provides self-alignment process, aggressive scaling, and uniformity. First of all, we have simulated to compare the characteristics between asymmetric and symmetric MOSFETs. Basically, both asymmetric and symmetric MOSFETs have an n-type channel (25-nm) and the same physical parameters. When we compare this with the 25-nm symmetric MOSFET, the proposed asymmetric MOSFET shows better device perfor
[1] Y. Murao,et al. An asymmetric sidewall process for high performance LDD MOSFET's , 1994 .
[2] C. Hu,et al. Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates , 1999 .
[3] Woo Young Choi,et al. Reverse-order source/drain formation with double offset spacer (RODOS) for low-power and high-speed application , 2003 .
[4] M. Lundstrom. Device physics at the scaling limit: what matters? [MOSFETs] , 2003, IEEE International Electron Devices Meeting 2003.