Instruction Code Compression for Application Specific VLIW Processors Based on Automatic Field Partitioning

This paper presents a method of reducing the instruction memory size of application specific VLIW processors. Given an object code of a processor, we try to compress it by recoding each instruction word with a smaller number of bits. The problem of finding a good coding which achieves large reduction and yet curbs the size and the delay of the decoder is reduced to the problem of finding a good field partitioning. By establishing a relation between a field partition and the cost of the program and decoders, we formulate an optimum field partitioning problem in which a field partition minimizing the cost of the program and the decoder is sought. We have developed an approximation algorithm to solve this problem. In a preliminary experiment on three sets of practical VLIW processors and application programs, the total objective cost, which is defined as the sum of the total bits of the coded program and the size of the ROMs to implement the decoder, is reduced into 46%∼60% of the original ones.