SAR Imaging Realization with FPGA Based on VIVADO HLS

Synthetic aperture radar (SAR) system develops with multiple modes, high resolution and wide range as a result of the increasing demand for aerial remote sensing in military and civilian fields. In terms of accuracy and quality, Omega-K algorithm is significantly more advantageous than other imaging algorithms. STOLT interpolation, as the core of Omega-K algorithm, features tremendous operations and high complexity. Traditional hardware description language (HDL) cannot satisfy current engineering requirements due to its weak ability of expression by algorithm, long programming cycle, and low efficiency of simulation verification. For this reason, this paper puts forward an approach of realizing Omega-K algorithm based on high-level synthesis (HLS). Considering the characteristics of Omega-K algorithm, HLS is employed for design of parallel processing architecture and optimization of array storage and flow processing to efficiently realize Omega-K algorithm on the field programmable gate array (FPGA) processing platform and eventually achieve airborne high-accuracy SAR imaging.