Input and output encoding techniques for on-line error detection in combinational logic circuits
暂无分享,去创建一个
[1] Alexander Saldanha,et al. Is redundancy necessary to reduce delay? , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Robert K. Brayton,et al. Multi-level logic minimization using implicit don't cares , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[3] Y. Savaria,et al. Soft-error filtering: A solution to the reliability problem of future VLSI digital circuits , 1986, Proceedings of the IEEE.
[4] Hao Dong. Modified Berger Codes for Detection of Unidirectional Errors , 1984, IEEE Trans. Computers.
[5] Srinivas Devadas,et al. Exact algorithms for output encoding, state assignment, and four-level Boolean minimization , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[6] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[7] Kurt Keutzer,et al. A unified approach to the synthesis of fully testable sequential machines , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Charles V. Freiman. Optimal Error Detection Codes for Completely Asymmetric Binary Channels , 1962, Inf. Control..
[9] Alberto L. Sangiovanni-Vincentelli,et al. Irredundant sequential machines via optimal logic synthesis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..