Toward understanding "Iddq-only" fails
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[1] A.D. Singh,et al. IDDQ testing of CMOS opens: an experimental study , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).
[2] Wojciech Maly,et al. Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.
[3] Víctor H. Champac,et al. CURRENT VS. LOGIC TESTING OF GATE OXIDE SHORT, FLOATING GATE AND BRIDGING FAILURES IN CMOS , 1991, 1991, Proceedings. International Test Conference.
[4] Wojciech Maly,et al. Current signatures: application , 1997, Proceedings International Test Conference 1997.
[5] Edward J. McCluskey,et al. Analysis of Gate Oxide Shorts in CMOS Circuits , 1993, IEEE Trans. Computers.
[6] F. Joel Ferguson,et al. Sandia National Labs , 2022 .
[7] Wojciech Maly,et al. Current signatures for integrated circuit test strategy advisor , 1998 .
[8] Charles F. Hawkins,et al. Electrical Characteristics and Testing Considerations for Gate Oxide Shorts in CMOS ICs , 1985, ITC.
[9] Edward J. McCluskey,et al. "RESISTIVE SHORTS" WITHIN CMOS GATES , 1991, 1991, Proceedings. International Test Conference.
[10] Rosa Rodríguez-Montañés,et al. Bridges in sequential CMOS circuits: current-voltage signature , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[11] R. Keith Treece,et al. CMOS IC stuck-open-fault electrical effects and design considerations , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[12] Wojciech Maly,et al. Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[13] Kenneth M. Butler,et al. So what is an optimal test mix? A discussion of the SEMATECH methods experiment , 1997, Proceedings International Test Conference 1997.
[14] P. Nigh,et al. An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[15] Edward J. McCluskey,et al. Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).