ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) in a 0.25-/spl mu/m salicided CMOS process

ESD protection design for high-speed I/O interface of stub series terminated logic (SSTL) is proposed. The SSTL I/O buffer with the proposed ESD protection design, which is designed to operate with a clock of 400 MHz, has been fabricated and verified in a 0.25-/spl mu/m salicided CMOS process. The human-body-model (HBM) and machine-model (MM) ESD levels of this SSTL I/O buffer can be greater than 8 kV and 750 V, respectively. Based on the excellent ESD performance, one set of area-efficient I/O cell library for SSTL in 1.8 V applications with this ESD protection design has been built up in a 0.25-/spl mu/m salicided CMOS process.