BiCMOS Digital Circuit Applications

In this chapter we study the application of BiCMOS digital circuits in the implementation of building blocks such as adders, ALU’s, memories, PLA’s and standard cells. The objective is to identify some of the applications where the BiCMOS can be useful. We will consider different design styles for BiCMOS circuits.

[1]  Douglas D. Smith,et al.  A 12-ns ECL I/O 256 K*1-bit SRAM using a 1- mu m BiCMOS technology , 1988 .

[2]  Kiyoo Itoh,et al.  A 1-Mbit BiCMOS DRAM using Temperature Compensation Circuit Techniques , 1988, ESSCIRC '88: Fourteenth European Solid-State Circuits Conference.

[3]  I. Masuda,et al.  High-speed BiCMOS technology with a buried twin well structure , 1987, IEEE Transactions on Electron Devices.

[4]  A. El Gamal,et al.  BiNMOS: a basic cell for BiCMOS sea-of-gates , 1989, 1989 Proceedings of the IEEE Custom Integrated Circuits Conference.

[5]  Makoto Suzuki,et al.  A 3.5 ns, 500 mW 16 kb BiCMOS ECL RAM , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[6]  K. Itoh Trends in megabit DRAM circuit design , 1990 .

[7]  Alan Jay Smith,et al.  Cache Memories , 1982, CSUR.

[8]  K. Nakamura,et al.  A 5 ns 1 Mb ECL BiCMOS SRAM , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[9]  Michel Declercq,et al.  Strategies for CMOS/BiCMOS gate usage on sea-of-gates arrays , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[10]  Tadashi Okamoto,et al.  A 32-bit CMOS microprocessor with on-chip cache and TLB , 1987 .

[11]  Kiyoo Itoh,et al.  An experimental 1-Mbit BiCMOS DRAM , 1987 .

[12]  C.H. Sequin,et al.  A 32-bit NMOS microprocessor with a large register file , 1984, IEEE Journal of Solid-State Circuits.

[13]  Robert W. Dutton,et al.  A single-ended BiCMOS sense circuit for digital circuits , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[14]  Koichiro Mashiko,et al.  A bipolar-PMOS merged basic cell for 0.8 mu m BiCMOS sea of gates , 1991 .

[15]  James D. Gallia,et al.  High-performance BiCMOS 100 K-gate array , 1990 .

[16]  Tatsumi Yamauchi,et al.  1.3- mu m CMOS/bipolar standard cell library for VLSI computers , 1988 .

[17]  Makoto Suzuki,et al.  A 7-ns/350-mW 64-kbit ECL-compatible RAM , 1987 .

[18]  Takayuki Kawahara,et al.  Comparison of CMOS and BiCMOS 1-Mbit DRAM performance , 1989 .

[19]  Yasuo Ohmori,et al.  BiCMOS circuit technology for a high speed SRAM , 1987, 1987 Symposium on VLSI Circuits.

[20]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[21]  S. Watanabe,et al.  BICMOS circuit technology for high speed DRAMs , 1987, 1987 Symposium on VLSI Circuits.

[22]  I. Masuda,et al.  Perspective on BiCMOS VLSIs , 1988 .

[23]  R. Krebs,et al.  A 3.8-ns 16 K BiCMOS SRAM , 1990 .

[24]  Goro Kitsukawa,et al.  A 23-ns 1-Mb BiCMOS DRAM , 1990 .

[25]  Masahiro Ueno,et al.  Very high‐speed ROM using bipolar/CMOS technology , 1988 .

[26]  R. Krebs,et al.  Merged CMOS/bipolar current switch logic (MCSL) , 1989 .

[27]  Ashwin H. Shah,et al.  An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capability , 1988 .

[28]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .